Apple-2-SW/prog8
1
0
Fork 0
mirror of https://github.com/irmen/prog8.git synced 2025-07-16 13:24:07 +00:00
Code Issues Projects Releases Wiki Activity

refactor IR returnregs

Browse Source
This commit is contained in:
Irmen de Jong
2023-03-13 00:32:48 +01:00
parent c12bf991b3
commit 1fdee861e8
4 changed files with 1044 additions and 786 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt
View File

@@ -142,13 +142,15 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
// calculate the assignment value
if (vmDt == IRDataType.FLOAT) {
resultFpRegister = codeGen.registers.nextFreeFloat()
result += expressionEval.translateExpression(assignment.value, -1, resultFpRegister)
val tr = expressionEval.translateExpression(assignment.value, -1, resultFpRegister)
addToResult(result, tr, -1, resultFpRegister)
} else {
resultRegister = if (assignment.value is PtMachineRegister) {
(assignment.value as PtMachineRegister).register
} else {
val reg = codeGen.registers.nextFree()
result += expressionEval.translateExpression(assignment.value, reg, -1)
val tr = expressionEval.translateExpression(assignment.value, reg, -1)
addToResult(result, tr, reg, -1)
reg
}
}
@@ -176,7 +178,8 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
if(array.index.type!=DataType.UBYTE)
throw AssemblyError("non-array var indexing requires bytes index")
val idxReg = codeGen.registers.nextFree()
result += expressionEval.translateExpression(array.index, idxReg, -1)
val tr = expressionEval.translateExpression(array.index, idxReg, -1)
addToResult(result, tr, idxReg, -1)
val code = IRCodeChunk(null, null)
if(zero) {
// there's no STOREZIX instruction
@@ -232,7 +235,8 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
result += chunk
} else {
val addressReg = codeGen.registers.nextFree()
result += expressionEval.translateExpression(memory.address, addressReg, -1)
val tr = expressionEval.translateExpression(memory.address, addressReg, -1)
addToResult(result, tr, addressReg, -1)
result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, vmDt, reg1=addressReg) }
}
} else {
@@ -241,7 +245,8 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
result += chunk
} else {
val addressReg = codeGen.registers.nextFree()
result += expressionEval.translateExpression(memory.address, addressReg, -1)
val tr = expressionEval.translateExpression(memory.address, addressReg, -1)
addToResult(result, tr, addressReg, -1)
result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, vmDt, reg1=resultRegister, reg2=addressReg) }
}
}
@@ -253,7 +258,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
}
private fun loadIndexReg(array: PtArrayIndexer, itemsize: Int, indexReg: Int): IRCodeChunks {
return if(itemsize==1) {
val tr = if(itemsize==1) {
expressionEval.translateExpression(array.index, indexReg, -1)
} else {
val mult = PtBinaryExpression("*", DataType.UBYTE, array.position)
@@ -261,5 +266,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
mult.children += PtNumber(DataType.UBYTE, itemsize.toDouble(), array.position)
expressionEval.translateExpression(mult, indexReg, -1)
}
require(tr.resultReg==indexReg && tr.resultFpReg==-1) // TODO weg
return tr.chunks
}
}