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fixed memory pointer access asm code for direct reads and direct assignments

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Irmen de Jong 2020-03-26 19:20:39 +01:00
parent 5f3a9e189a
commit 22f8f4f359
1 changed files with 28 additions and 33 deletions
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61
compiler/src/prog8/compiler/target/c64/codegen/AssignmentAsmGen.kt
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@ -426,31 +426,23 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
val targetName = asmgen.asmIdentifierName(addressExpr) val targetName = asmgen.asmIdentifierName(addressExpr)
when(register) { when(register) {
Register.A -> asmgen.out(""" Register.A -> asmgen.out("""
ldy $targetName ldy $targetName
sty ${C64Zeropage.SCRATCH_W1} sty (+) +1
ldy $targetName+1 ldy $targetName+1
sty ${C64Zeropage.SCRATCH_W1+1} sty (+) +2
ldy #0 + sta ${'$'}ffff ; modified""")
sta (${C64Zeropage.SCRATCH_W1}),y
""")
Register.X -> asmgen.out(""" Register.X -> asmgen.out("""
txa ldy $targetName
ldy $targetName sty (+) +1
sty ${C64Zeropage.SCRATCH_W1} ldy $targetName+1
ldy $targetName+1 sty (+) +2
sty ${C64Zeropage.SCRATCH_W1+1} + stx ${'$'}ffff ; modified""")
ldy #0
sta (${C64Zeropage.SCRATCH_W1}),y
""")
Register.Y -> asmgen.out(""" Register.Y -> asmgen.out("""
tya lda $targetName
ldy $targetName sta (+) +1
sty ${C64Zeropage.SCRATCH_W1} lda $targetName+1
ldy $targetName+1 sta (+) +2
sty ${C64Zeropage.SCRATCH_W1+1} + sty ${'$'}ffff ; modified""")
ldy #0
sta (${C64Zeropage.SCRATCH_W1}),y
""")
} }
} }
else -> { else -> {
@ -696,22 +688,25 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
when { when {
target.register!=null -> { target.register!=null -> {
asmgen.out(""" asmgen.out("""
ldy #0 lda $sourceName
lda ($sourceName),y sta (+) + 1
""") lda $sourceName+1
sta (+) + 2""")
when(target.register){ when(target.register){
Register.A -> {} Register.A -> asmgen.out("+ lda ${'$'}ffff\t; modified")
Register.X -> asmgen.out(" tax") Register.X -> asmgen.out("+ ldx ${'$'}ffff\t; modified")
Register.Y -> asmgen.out(" tay") Register.Y -> asmgen.out("+ ldy ${'$'}ffff\t; modified")
} }
} }
targetIdent!=null -> { targetIdent!=null -> {
val targetName = asmgen.asmIdentifierName(targetIdent) val targetName = asmgen.asmIdentifierName(targetIdent)
asmgen.out(""" asmgen.out("""
ldy #0 lda $sourceName
lda ($sourceName),y sta (+) + 1
sta $targetName lda $sourceName+1
""") sta (+) + 2
+ lda ${'$'}ffff\t; modified
sta $targetName""")
} }
target.memoryAddress!=null -> { target.memoryAddress!=null -> {
asmgen.out(" ldy $sourceName") asmgen.out(" ldy $sourceName")