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optimize RPN
This commit is contained in:
Irmen de Jong
parent
c66734bab0
commit
2afd283582
@ -373,11 +373,16 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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return true
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return true
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}
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}
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if(value.children.size==3 && left is PtExpression && right is PtExpression)
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if(value.children.size==3 && left is PtExpression && right is PtExpression) {
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if(simpleLogicalExprRPN(left, oper.operator, right, assign.target))
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if (simpleEqualityExprRPN(left, oper.operator, right, assign.target))
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return true
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return true
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if (simpleLogicalExprRPN(left, oper.operator, right, assign.target))
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// TODO RPN add +,-,<<,>> and perhaps even == and != special behaviors of BinExpr
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return true
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if (simplePlusOrMinusExprRPN(left, oper.operator, right, assign.target))
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return true
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if (simpleBitshiftExprRPN(left, oper.operator, right, assign.target))
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return true
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}
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val asmExtra = asmgen.subroutineExtra(scope)
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val asmExtra = asmgen.subroutineExtra(scope)
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val evalVars = mutableMapOf (
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val evalVars = mutableMapOf (
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@ -554,6 +559,264 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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return false
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return false
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}
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}
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private fun simpleEqualityExprRPN(left: PtExpression, operator: String, right: PtExpression, target: AsmAssignTarget): Boolean {
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if(operator!="==" && operator!="!=")
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return false
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// expression datatype is BOOL (ubyte) but operands can be anything
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if(left.type in ByteDatatypes && right.type in ByteDatatypes &&
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left.isSimple() && right.isSimple()) {
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assignExpressionToRegister(left, RegisterOrPair.A, false)
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asmgen.saveRegisterStack(CpuRegister.A, false)
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assignExpressionToVariable(right, "P8ZP_SCRATCH_B1", DataType.UBYTE)
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asmgen.restoreRegisterStack(CpuRegister.A, false)
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if(operator=="==") {
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asmgen.out("""
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cmp P8ZP_SCRATCH_B1
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bne +
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lda #1
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bne ++
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+ lda #0
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+""")
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} else {
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asmgen.out("""
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cmp P8ZP_SCRATCH_B1
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beq +
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lda #1
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bne ++
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+ lda #0
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+""")
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}
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assignRegisterByte(target, CpuRegister.A)
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return true
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} else if(left.type in WordDatatypes && right.type in WordDatatypes &&
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left.isSimple() && right.isSimple()) {
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assignExpressionToRegister(left, RegisterOrPair.AY, false)
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asmgen.saveRegisterStack(CpuRegister.A, false)
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asmgen.saveRegisterStack(CpuRegister.Y, false)
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assignExpressionToVariable(right, "P8ZP_SCRATCH_W1", DataType.UWORD)
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asmgen.restoreRegisterStack(CpuRegister.Y, false)
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asmgen.restoreRegisterStack(CpuRegister.A, false)
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if(operator=="==") {
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asmgen.out("""
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cmp P8ZP_SCRATCH_W1
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bne +
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cpy P8ZP_SCRATCH_W1+1
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bne +
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lda #1
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bne ++
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+ lda #0
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+""")
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} else {
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asmgen.out("""
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cmp P8ZP_SCRATCH_W1
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bne +
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cpy P8ZP_SCRATCH_W1+1
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bne +
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lda #0
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bne ++
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+ lda #1
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+""")
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}
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assignRegisterByte(target, CpuRegister.A)
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return true
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}
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return false
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}
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private fun simplePlusOrMinusExprRPN(left: PtExpression, operator: String, right: PtExpression, target: AsmAssignTarget): Boolean {
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if(operator!="+" && operator!="!-")
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return false
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val dt = target.datatype
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if(dt in ByteDatatypes) {
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when (right) {
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is PtIdentifier -> {
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assignExpressionToRegister(left, RegisterOrPair.A, dt==DataType.BYTE)
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val symname = asmgen.asmVariableName(right)
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if(operator=="+")
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asmgen.out(" clc | adc $symname")
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else
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asmgen.out(" sec | sbc $symname")
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assignRegisterByte(target, CpuRegister.A)
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return true
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}
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is PtNumber -> {
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assignExpressionToRegister(left, RegisterOrPair.A, dt==DataType.BYTE)
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if(operator=="+")
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asmgen.out(" clc | adc #${right.number.toHex()}")
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else
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asmgen.out(" sec | sbc #${right.number.toHex()}")
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assignRegisterByte(target, CpuRegister.A)
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return true
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}
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else -> return false
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}
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} else if(dt in WordDatatypes) {
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when (right) {
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is PtAddressOf -> {
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assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
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val symbol = asmgen.asmVariableName(right.identifier)
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if(operator=="+")
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asmgen.out("""
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clc
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adc #<$symbol
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pha
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tya
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adc #>$symbol
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tay
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pla""")
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else
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asmgen.out("""
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sec
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sbc #<$symbol
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pha
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tya
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sbc #>$symbol
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tay
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pla""")
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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is PtIdentifier -> {
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val symname = asmgen.asmVariableName(right)
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assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
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if(operator=="+")
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asmgen.out("""
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clc
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adc $symname
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pha
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tya
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adc $symname+1
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tay
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pla""")
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else
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asmgen.out("""
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sec
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sbc $symname
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pha
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tya
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sbc $symname+1
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tay
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pla""")
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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is PtNumber -> {
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assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
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if(operator=="+") {
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asmgen.out("""
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clc
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adc #<${right.number.toHex()}
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pha
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tya
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adc #>${right.number.toHex()}
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tay
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pla""")
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} else if(operator=="-") {
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asmgen.out("""
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sec
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sbc #<${right.number.toHex()}
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pha
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tya
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sbc #>${right.number.toHex()}
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tay
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pla""")
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}
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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is PtTypeCast -> {
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val castedValue = right.value
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if(right.type in WordDatatypes && castedValue.type in ByteDatatypes) {
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if(castedValue is PtIdentifier) {
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val castedSymname = asmgen.asmVariableName(castedValue)
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assignExpressionToRegister(left, RegisterOrPair.AY, dt==DataType.WORD)
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if(operator=="+")
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asmgen.out("""
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clc
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adc $castedSymname
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bcc +
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iny
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+""")
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else
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asmgen.out("""
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sec
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sbc $castedSymname
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bcs +
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dey
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+""")
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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}
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}
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else -> return false
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}
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}
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return false
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}
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private fun simpleBitshiftExprRPN(left: PtExpression, operator: String, right: PtExpression, target: AsmAssignTarget): Boolean {
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if(operator!="<<" && operator!=">>")
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return false
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val shifts = right.asConstInteger()
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if(shifts!=null) {
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val dt = left.type
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if(dt in ByteDatatypes && shifts in 0..7) {
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val signed = dt == DataType.BYTE
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assignExpressionToRegister(left, RegisterOrPair.A, signed)
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if(operator=="<<") {
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repeat(shifts) {
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asmgen.out(" asl a")
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}
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} else {
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if(signed && shifts>0) {
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asmgen.out(" ldy #$shifts | jsr math.lsr_byte_A")
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} else {
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repeat(shifts) {
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asmgen.out(" lsr a")
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}
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}
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}
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assignRegisterByte(target, CpuRegister.A)
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return true
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} else if(dt in WordDatatypes && shifts in 0..7) {
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val signed = dt == DataType.WORD
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assignExpressionToRegister(left, RegisterOrPair.AY, signed)
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if(operator=="<<") {
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if(shifts>0) {
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asmgen.out(" sty P8ZP_SCRATCH_B1")
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repeat(shifts) {
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asmgen.out(" asl a | rol P8ZP_SCRATCH_B1")
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}
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asmgen.out(" ldy P8ZP_SCRATCH_B1")
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}
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} else {
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if(signed) {
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// TODO("shift AY >> $shifts signed")
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return false
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} else {
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if(shifts>0) {
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asmgen.out(" sty P8ZP_SCRATCH_B1")
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repeat(shifts) {
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asmgen.out(" lsr P8ZP_SCRATCH_B1 | ror a")
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}
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asmgen.out(" ldy P8ZP_SCRATCH_B1")
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}
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}
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}
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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}
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return false
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}
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private fun assignRPNComparison(assign: AsmAssignment, comparison: PtRpn) {
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private fun assignRPNComparison(assign: AsmAssignment, comparison: PtRpn) {
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val (leftRpn, oper, right) = comparison.finalOperation()
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val (leftRpn, oper, right) = comparison.finalOperation()
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val constRight = (right as PtExpression).asConstInteger()
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val constRight = (right as PtExpression).asConstInteger()
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@ -1,11 +1,13 @@
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TODO
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TODO
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====
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====
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RPN: Fix the TODO RPN routines to be optimized assembly in RpnExpressionAsmGen.kt
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RPN: cube3d-sprites compiler crash (bit shift too large)
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then:
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RPN: swirl is bigger and MUCH slower
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RPN: examples/bsieve,charset compilation crash (bit shift expression)
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RPN: wizzine is slower but about equal size
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RPN: charset is larger
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RPN: cube3d is much larger, but a bit faster
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RPN: cube3d-float is massive and slow
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RPN: cube3d-float is massive and slow
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RPN: mandelbrot is big, but seems faster
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RPN: mandelbrot is bigger, but seems faster
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RPN: swirl is MUCH slower, wizzine is slower
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then:
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then:
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RPN: Implement RPN codegen for IR.
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RPN: Implement RPN codegen for IR.
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