test

2026-04-25 12:33:55 +00:00 · 2025-08-19 23:09:33 +02:00
parent fc5889ec0b
commit 32e531f951
3 changed files with 31 additions and 9 deletions
@@ -1317,7 +1317,7 @@ internal class AssignmentAsmGen(
                        else
                            asmgen.out("  sec |  sbc  #${right.number.toHex()}")
                    }
-                    assignRegisterByte(target, CpuRegister.A, dt.isSigned, true)
+                    assignRegisterByte(target, CpuRegister.A, dt.isSigned, target.datatype.isWord)
                    return true
                }
                else -> {
@@ -3341,7 +3341,7 @@ $endLabel""")
                        RegisterOrPair.Y -> { asmgen.out("  tay") }
                        RegisterOrPair.AY -> {
                            require(extendWord) {
-                                "no extend"
+                                "no extend but byte target is registerpair"
                            }
                            if(signed)
                                asmgen.out("""