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https://github.com/irmen/prog8.git
synced 2024-11-26 11:49:22 +00:00
added irq routines for cx16
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0e62f5b759
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334f86480a
@ -294,6 +294,12 @@ asmsub init_system() {
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}}
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}
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asmsub init_system_phase2() {
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%asm {{
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rts ; no phase 2 steps on the C64
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}}
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}
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asmsub disable_runstop_and_charsetswitch() clobbers(A) {
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%asm {{
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lda #$80
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@ -410,7 +416,7 @@ asmsub set_rasterirq(uword handler @AY, uword rasterpos @R0, ubyte useKernal @P
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sty _modified+2
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lda #0
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adc #0
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sta _use_kernal
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sta set_irq._use_kernal
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lda cx16.r0
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ldy cx16.r0+1
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sei
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@ -422,15 +428,13 @@ asmsub set_rasterirq(uword handler @AY, uword rasterpos @R0, ubyte useKernal @P
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cli
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rts
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_use_kernal .byte 0
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_raster_irq_handler
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jsr set_irq._irq_handler_init
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_modified jsr $ffff ; modified
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jsr set_irq._irq_handler_end
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lda #$ff
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sta c64.VICIRQ ; acknowledge raster irq
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lda _use_kernal
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lda set_irq._use_kernal
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bne +
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; end irq processing - don't use kernal's irq handling
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pla
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@ -102,10 +102,11 @@ asmsub MEMTOP2() -> ubyte @A {
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cx16 {
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; 65c02 hardware vectors:
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&uword NMI_VEC = $FFFA ; 6502 nmi vector, determined by the kernal if banked in
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&uword RESET_VEC = $FFFC ; 6502 reset vector, determined by the kernal if banked in
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&uword IRQ_VEC = $FFFE ; 6502 interrupt vector, determined by the kernal if banked in
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; irq and hardware vectors:
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&uword CINV = $0314 ; IRQ vector (in ram)
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&uword NMI_VEC = $FFFA ; 65c02 nmi vector, determined by the kernal if banked in
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&uword RESET_VEC = $FFFC ; 65c02 reset vector, determined by the kernal if banked in
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&uword IRQ_VEC = $FFFE ; 65c02 interrupt vector, determined by the kernal if banked in
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; the sixteen virtual 16-bit registers
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@ -485,8 +486,166 @@ asmsub init_system() {
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}}
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}
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asmsub init_system_phase2() {
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%asm {{
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sei
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lda cx16.CINV
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sta restore_irq._orig_irqvec
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lda cx16.CINV+1
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sta restore_irq._orig_irqvec+1
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cli
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rts
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}}
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}
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asmsub set_irq(uword handler @AY, ubyte useKernal @Pc) clobbers(A) {
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%asm {{
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sta _modified+1
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sty _modified+2
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lda #0
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adc #0
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sta _use_kernal
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sei
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lda #<_irq_handler
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sta cx16.CINV
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lda #>_irq_handler
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sta cx16.CINV+1
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lda cx16.VERA_IEN
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ora #%00000001 ; enable the vsync irq
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sta cx16.VERA_IEN
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cli
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rts
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_irq_handler jsr _irq_handler_init
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_modified jsr $ffff ; modified
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jsr _irq_handler_end
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lda _use_kernal
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bne +
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; end irq processing - don't use kernal's irq handling
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lda cx16.VERA_ISR
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ora #1
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sta cx16.VERA_ISR ; clear Vera Vsync irq status
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ply
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plx
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pla
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rti
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+ jmp (restore_irq._orig_irqvec) ; continue with normal kernal irq routine
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_use_kernal .byte 0
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_irq_handler_init
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; save all zp scratch registers and the X register as these might be clobbered by the irq routine
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stx IRQ_X_REG
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lda P8ZP_SCRATCH_B1
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sta IRQ_SCRATCH_ZPB1
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lda P8ZP_SCRATCH_REG
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sta IRQ_SCRATCH_ZPREG
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lda P8ZP_SCRATCH_W1
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sta IRQ_SCRATCH_ZPWORD1
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lda P8ZP_SCRATCH_W1+1
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sta IRQ_SCRATCH_ZPWORD1+1
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lda P8ZP_SCRATCH_W2
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sta IRQ_SCRATCH_ZPWORD2
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lda P8ZP_SCRATCH_W2+1
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sta IRQ_SCRATCH_ZPWORD2+1
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; stack protector; make sure we don't clobber the top of the evaluation stack
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dex
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dex
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dex
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dex
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dex
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dex
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cld
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rts
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_irq_handler_end
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; restore all zp scratch registers and the X register
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lda IRQ_SCRATCH_ZPB1
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sta P8ZP_SCRATCH_B1
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lda IRQ_SCRATCH_ZPREG
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sta P8ZP_SCRATCH_REG
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lda IRQ_SCRATCH_ZPWORD1
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sta P8ZP_SCRATCH_W1
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lda IRQ_SCRATCH_ZPWORD1+1
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sta P8ZP_SCRATCH_W1+1
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lda IRQ_SCRATCH_ZPWORD2
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sta P8ZP_SCRATCH_W2
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lda IRQ_SCRATCH_ZPWORD2+1
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sta P8ZP_SCRATCH_W2+1
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ldx IRQ_X_REG
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rts
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IRQ_X_REG .byte 0
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IRQ_SCRATCH_ZPB1 .byte 0
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IRQ_SCRATCH_ZPREG .byte 0
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IRQ_SCRATCH_ZPWORD1 .word 0
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IRQ_SCRATCH_ZPWORD2 .word 0
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}}
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}
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asmsub restore_irq() clobbers(A) {
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%asm {{
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sei
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lda _orig_irqvec
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sta cx16.CINV
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lda _orig_irqvec+1
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sta cx16.CINV+1
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lda cx16.VERA_IEN
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and #%11110000 ; disable all Vera IRQs
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ora #%00000001 ; enable only the vsync Irq
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sta cx16.VERA_IEN
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cli
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rts
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_orig_irqvec .word 0
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}}
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}
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asmsub set_rasterirq(uword handler @AY, uword rasterpos @R0) clobbers(A) {
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%asm {{
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sta _modified+1
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sty _modified+2
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lda cx16.r0
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ldy cx16.r0+1
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sei
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lda cx16.VERA_IEN
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and #%11110000 ; clear other IRQs
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ora #%00000010 ; enable the line (raster) irq
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sta cx16.VERA_IEN
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lda cx16.r0
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sta cx16.VERA_IRQ_LINE_L
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lda cx16.r0+1
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lsr a
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ror a
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and #%10000000
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ora cx16.VERA_IEN
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sta cx16.VERA_IEN ; high bit of the raster line
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lda #<_raster_irq_handler
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sta cx16.CINV
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lda #>_raster_irq_handler
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sta cx16.CINV+1
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cli
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rts
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_raster_irq_handler
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jsr set_irq._irq_handler_init
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_modified jsr $ffff ; modified
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jsr set_irq._irq_handler_end
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; end irq processing - don't use kernal's irq handling
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lda cx16.VERA_ISR
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ora #%00000010
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sta cx16.VERA_ISR ; clear Vera line irq status
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ply
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plx
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pla
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rti
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}}
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}
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}
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sys {
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; ------- lowlevel system routines --------
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@ -133,12 +133,14 @@ internal class AsmGen(private val program: Program,
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out("_prog8_entrypoint\t; assembly code starts here\n")
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if(!options.noSysInit)
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out(" jsr ${compTarget.name}.init_system")
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out(" jsr ${compTarget.name}.init_system_phase2")
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}
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options.output == OutputType.PRG -> {
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out("; ---- program without basic sys call ----")
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out("* = ${program.actualLoadAddress.toHex()}\n")
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if(!options.noSysInit)
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out(" jsr ${compTarget.name}.init_system")
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out(" jsr ${compTarget.name}.init_system_phase2")
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}
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options.output == OutputType.RAW -> {
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out("; ---- raw assembler program ----")
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@ -148,3 +148,8 @@ For the C64 these routines are::
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c64.set_rasterirq(uword handler_address, uword rasterline, boolean useKernal)
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c64.restore_irq() ; set everything back to the systems default irq handler
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And for the Commander X16:
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cx16.set_irq(uword handler_address, boolean useKernal) ; vsync irq
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cx16.set_rasterirq(uword handler_address, uword rasterline) ; note: disables kernal irq handler! sys.wait() won't work anymore
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cx16.restore_irq() ; set everything back to the systems default irq handler
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@ -7,17 +7,10 @@ main {
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; $1F9C0 - $1F9FF PSG registers
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sub start() {
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uword color=0
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repeat {
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cx16.vpoke(1, $fa00+6*2, lsb(color))
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cx16.vpoke(1, $fa01+6*2, msb(color))
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color++
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}
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;c64.set_rasterirq(&irq.irq, 100, true)
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cx16.set_rasterirq(&irq.irq, 100)
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;cx16.set_irq(&irq.irq, true)
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sys.wait(100)
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;c64.restore_irq()
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cx16.restore_irq()
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; uword freq = 1181
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; cx16.vpoke(1, $f9c0, lsb(freq))
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@ -29,10 +22,26 @@ main {
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irq {
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%option force_output
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uword counter = 0
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sub irq() {
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cx16.vpoke(1, $fa00+6*2, lsb(counter))
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cx16.vpoke(1, $fa01+6*2, msb(counter))
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repeat 20 {
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uword xx
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repeat 16 {
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xx++
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}
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cx16.vpoke(1, $fa00+6*2, 0)
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cx16.vpoke(1, $fa01+6*2, 255)
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repeat 16 {
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xx++
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}
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cx16.vpoke(1, $fa00+6*2, 0)
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cx16.vpoke(1, $fa01+6*2, 0)
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}
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counter++
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}
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}
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