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IR: added SCC and SCS instructions

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This commit is contained in:
Irmen de Jong 2024-01-09 00:57:02 +01:00
parent aa4cd13c31
commit 38dc7fb7bd
4 changed files with 21 additions and 8 deletions
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10
compiler/res/prog8lib/virtual/monogfx.p8
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@ -70,12 +70,9 @@ monogfx {
}
sub horizontal_line(uword xx, uword yy, uword length, bool draw) {
ubyte color = 0
if draw
color = 255
uword xpos
for xpos in xx to xx+length-1
plot(xpos, yy, color)
plot(xpos, yy, draw)
}
sub safe_horizontal_line(uword xx, uword yy, uword length, bool draw) {
@ -97,12 +94,9 @@ monogfx {
}
sub vertical_line(uword xx, uword yy, uword lheight, bool draw) {
ubyte color = 0
if draw
color = 255
uword ypos
for ypos in yy to yy+lheight-1
plot(xx, ypos, color)
plot(xx, ypos, draw)
}
sub line(uword @zp x1, uword @zp y1, uword @zp x2, uword @zp y2, bool draw) {

1
docs/source/todo.rst
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@ -1,6 +1,7 @@
TODO
====
IR: use SCC and SCS, to optimize some code that sets 0/1 based on carry flag status
...

6
intermediate/src/prog8/intermediate/IRInstructions.kt
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@ -106,6 +106,8 @@ bles reg1, value, address - jump to location in program given by l
bgesr reg1, reg2, address - jump to location in program given by location, if reg1 >= reg2 (signed)
'blesr' reg1, reg2, address - jump to location in program given by location, if reg1 <= reg2 (signed) ==> use bgesr with swapped operands
scc reg1 - set reg1=1 if Carry flag is clear, else 0
scs reg1 - set reg1=1 if Carry flag is set, else 0
sz reg1, reg2 - set reg1=1 if reg2==0, else 0
snz reg1, reg2 - set reg1=1 if reg2!=0, else 0
seq reg1, reg2, reg3 - set reg1=1 if reg2 == reg3, else 0
@ -280,6 +282,8 @@ enum class Opcode {
BGESR,
BGES,
BLES,
SCC,
SCS,
SZ,
SNZ,
SEQ,
@ -593,6 +597,8 @@ val instructionFormats = mutableMapOf(
Opcode.BGESR to InstructionFormat.from("BW,<r1,<r2,<a"),
Opcode.BGES to InstructionFormat.from("BW,<r1,<i,<a"),
Opcode.BLES to InstructionFormat.from("BW,<r1,<i,<a"),
Opcode.SCC to InstructionFormat.from("BW,>r1"),
Opcode.SCS to InstructionFormat.from("BW,>r1"),
Opcode.SZ to InstructionFormat.from("BW,>r1,<r2"),
Opcode.SNZ to InstructionFormat.from("BW,>r1,<r2"),
Opcode.SEQ to InstructionFormat.from("BW,<>r1,<r2,<r3"),

12
virtualmachine/src/prog8/vm/VirtualMachine.kt
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@ -203,6 +203,8 @@ class VirtualMachine(irProgram: IRProgram) {
Opcode.BLE -> InsBLE(ins)
Opcode.BGES -> InsBGES(ins)
Opcode.BLES -> InsBLES(ins)
Opcode.SCC -> InsSCC(ins)
Opcode.SCS -> InsSCS(ins)
Opcode.SZ -> InsSZ(ins)
Opcode.SNZ -> InsSNZ(ins)
Opcode.SEQ -> InsSEQ(ins)
@ -771,6 +773,16 @@ class VirtualMachine(irProgram: IRProgram) {
nextPc()
}
private fun InsSCC(i: IRInstruction) {
setResultReg(i.reg1!!, if(statusCarry) 0 else 1, i.type!!)
nextPc()
}
private fun InsSCS(i: IRInstruction) {
setResultReg(i.reg1!!, if(statusCarry) 1 else 0, i.type!!)
nextPc()
}
private fun InsSZ(i: IRInstruction) {
val right = when(i.type) {
IRDataType.BYTE -> registers.getSB(i.reg2!!).toInt()