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https://github.com/irmen/prog8.git
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IR: implemented inplace prefix op on split array
VM: NEG instructions also set N and Z flags
This commit is contained in:
Irmen de Jong
parent
0800033b47
commit
39d2194d8f
@ -36,8 +36,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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else
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fallbackAssign(augAssign)
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} else if(array!=null) {
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// TODO assignArrayAugmented(array, augAssign)
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fallbackAssign(augAssign)
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assignArrayAugmented(array, augAssign)
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} else {
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fallbackAssign(augAssign)
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}
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@ -157,27 +156,84 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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}
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private fun inplacePrefix(operator: String, array: PtArrayIndexer, eltSize: Int): Result<IRCodeChunks, NotImplementedError> {
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if(array.splitWords)
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TODO("inplace prefix for split word array")
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val result = mutableListOf<IRCodeChunkBase>()
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val vmDt = irType(array.type)
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val constIndex = array.index.asConstInteger()
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fun loadIndex(): Int {
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val tr = expressionEval.translateExpression(array.index)
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addToResult(result, tr, tr.resultReg, -1)
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if(!array.splitWords && eltSize>1)
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result += codeGen.multiplyByConst(IRDataType.BYTE, tr.resultReg, eltSize)
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return tr.resultReg
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}
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if(array.splitWords) {
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// handle split LSB/MSB arrays
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when(operator) {
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"+" -> { }
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"-" -> {
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val skipCarryLabel = codeGen.createLabelName()
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if(constIndex!=null) {
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addInstr(result, IRInstruction(Opcode.NEGM, IRDataType.BYTE, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex), null)
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addInstr(result, IRInstruction(Opcode.BSTEQ, labelSymbol = skipCarryLabel), null)
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addInstr(result, IRInstruction(Opcode.INCM, IRDataType.BYTE, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex), null)
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addInstr(result, IRInstruction(Opcode.NEGM, IRDataType.BYTE, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex), skipCarryLabel)
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} else {
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val indexReg = loadIndex()
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val registerLsb = codeGen.registers.nextFree()
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val registerMsb = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1 = registerLsb, reg2 = indexReg, labelSymbol = array.variable.name+"_lsb")
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it += IRInstruction(Opcode.NEG, IRDataType.BYTE, reg1 = registerLsb)
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it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = registerLsb, reg2 = indexReg, labelSymbol = array.variable.name+"_lsb")
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1 = registerMsb, reg2 = indexReg, labelSymbol = array.variable.name+"_msb")
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it += IRInstruction(Opcode.NEG, IRDataType.BYTE, reg1 = registerMsb)
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it += IRInstruction(Opcode.CMPI, IRDataType.BYTE, reg1 = registerLsb, immediate = 0)
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it += IRInstruction(Opcode.BSTEQ, labelSymbol = skipCarryLabel)
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it += IRInstruction(Opcode.DEC, IRDataType.BYTE, reg1 = registerMsb)
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}
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result += IRCodeChunk(skipCarryLabel, null).also {
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it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = registerMsb, reg2 = indexReg, labelSymbol = array.variable.name+"_msb")
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}
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}
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}
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"~" -> {
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if(constIndex!=null) {
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addInstr(result, IRInstruction(Opcode.INVM, IRDataType.BYTE, labelSymbol = array.variable.name+"_lsb", symbolOffset = constIndex), null)
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addInstr(result, IRInstruction(Opcode.INVM, IRDataType.BYTE, labelSymbol = array.variable.name+"_msb", symbolOffset = constIndex), null)
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} else {
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val indexReg = loadIndex()
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val register = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name+"_lsb")
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it += IRInstruction(Opcode.INV, IRDataType.BYTE, reg1 = register)
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it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name+"_lsb")
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it += IRInstruction(Opcode.LOADX, IRDataType.BYTE, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name+"_msb")
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it += IRInstruction(Opcode.INV, IRDataType.BYTE, reg1 = register)
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it += IRInstruction(Opcode.STOREX, IRDataType.BYTE, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name+"_msb")
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}
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}
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}
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else -> throw AssemblyError("weird prefix operator")
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}
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return Ok(result)
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}
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// normal array.
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when(operator) {
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"+" -> { }
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"-" -> {
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if(constIndex!=null) {
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addInstr(result, IRInstruction(Opcode.NEGM, vmDt, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize), null)
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} else {
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val indexReg = loadIndex()
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val register = codeGen.registers.nextFree()
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val tr = expressionEval.translateExpression(array.index)
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addToResult(result, tr, tr.resultReg, -1)
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if(eltSize>1)
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result += codeGen.multiplyByConst(IRDataType.BYTE, tr.resultReg, eltSize)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADX, vmDt, reg1 = register, reg2 = tr.resultReg, labelSymbol = array.variable.name)
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it += IRInstruction(Opcode.LOADX, vmDt, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name)
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it += IRInstruction(Opcode.NEG, vmDt, reg1 = register)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1 = register, reg2 = tr.resultReg, labelSymbol = array.variable.name)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name)
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}
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}
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}
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@ -185,35 +241,29 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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if(constIndex!=null) {
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addInstr(result, IRInstruction(Opcode.INVM, vmDt, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize), null)
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} else {
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val indexReg = loadIndex()
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val register = codeGen.registers.nextFree()
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val tr = expressionEval.translateExpression(array.index)
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addToResult(result, tr, tr.resultReg, -1)
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if(eltSize>1)
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result += codeGen.multiplyByConst(IRDataType.BYTE, tr.resultReg, eltSize)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADX, vmDt, reg1 = register, reg2 = tr.resultReg, labelSymbol = array.variable.name)
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it += IRInstruction(Opcode.LOADX, vmDt, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name)
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it += IRInstruction(Opcode.INV, vmDt, reg1 = register)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1 = register, reg2 = tr.resultReg, labelSymbol = array.variable.name)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name)
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}
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}
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}
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"not" -> {
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// TODO: in boolean branch, is 'not' handled ok like this?
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val register = codeGen.registers.nextFree()
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if(constIndex!=null) {
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// TODO: in boolean branch, is 'not' handled ok like this?
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, vmDt, reg1=register, immediate = 1)
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it += IRInstruction(Opcode.XORM, vmDt, reg1=register, labelSymbol = array.variable.name, symbolOffset = constIndex*eltSize)
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}
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} else {
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val tr = expressionEval.translateExpression(array.index)
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addToResult(result, tr, tr.resultReg, -1)
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if(eltSize>1)
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result += codeGen.multiplyByConst(IRDataType.BYTE, tr.resultReg, eltSize)
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val indexReg = loadIndex()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADX, vmDt, reg1 = register, reg2 = tr.resultReg, labelSymbol = array.variable.name)
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it += IRInstruction(Opcode.LOADX, vmDt, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name)
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it += IRInstruction(Opcode.XOR, vmDt, reg1 = register, immediate = 1)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1 = register, reg2 = tr.resultReg, labelSymbol = array.variable.name)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1 = register, reg2 = indexReg, labelSymbol = array.variable.name)
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}
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}
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}
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@ -5,43 +5,27 @@
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main {
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sub start() {
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ubyte @shared index = 1
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word[3] @split @shared array = [1111,$10ff,3333]
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; @(2000) = 99
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; uword @shared ptr = 2000
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; txt.print_ub(@(2000))
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; txt.nl()
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; @(2000) ++
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; @(2000) ++
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; @(2000) --
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; txt.print_ub(@(2000))
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; txt.nl()
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uword[3] @split arr
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arr[1] = 9999
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txt.print_uw(arr[1])
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txt.print_w(array[1])
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txt.nl()
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txt.print_w(-array[1])
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txt.nl()
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array[1] = -array[1]
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txt.print_w(array[1])
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txt.nl()
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arr[1] = arr[1]*5
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cx16.r0=2222
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arr[1] *= cx16.r0
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arr[1] -=5
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arr[1] -=index
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txt.print_uw(arr[1])
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txt.nl()
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; arr[index] = 9999
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; txt.print_uw(arr[index])
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; txt.nl()
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; arr[index] += 5
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; arr[index] += 5
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; arr[index] -= 5
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; txt.print_uw(arr[index])
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; txt.nl()
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ubyte @shared idx = 1
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txt.print_w(array[idx])
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txt.nl()
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txt.print_w(-array[idx])
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txt.nl()
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array[idx] = -array[idx]
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txt.print_w(array[idx])
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txt.nl()
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;
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; ubyte @shared xx
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; uword[3] ubarr
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; bool[3] barr
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@ -52,20 +36,20 @@ main {
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; ubarr[1] = ubarr[1] <= 2
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; ubarr[1] = ubarr[1] > 3
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; ubarr[1] = ubarr[1] >= 3
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;
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; barr[1] = barr[0] and barr[2]
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; barr[1] = barr[0] or barr[2]
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; barr[1] = barr[0] xor barr[2]
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; barr[1] = not barr[0]
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;
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; ubarr[1] = 999
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; ubarr[1] = ubarr[1]==999
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; txt.print_uw(ubarr[1])
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;
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; barr[1] = barr[1] and bb
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; barr[1] = barr[1] or bb
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; barr[1] = barr[1] xor bb
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;
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; bb = bb and barr[1]
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; bb = bb or barr[1]
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; bb = bb xor barr[1]
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@ -16,7 +16,7 @@ Program to execute is not stored in the system memory, it's just a separate list
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Value stack, max 128 entries of 1 byte each.
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Status flags: Carry, Zero, Negative. NOTE: status flags are only affected by the CMP instruction or explicit CLC/SEC,
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LOAD instructions DO affect the Z and N flags.
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INC/DEC instructions DO affect the Z and N flags,
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INC/DEC/NEG instructions DO affect the Z and N flags,
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other instructions only affect Z an N flags if the value in a result register is written.
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See OpcodesThatSetStatusbits
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@ -444,6 +444,8 @@ val OpcodesThatSetStatusbitsButNotCarry = arrayOf(
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Opcode.LOADX,
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Opcode.LOADIX,
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Opcode.LOADR,
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Opcode.NEG,
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Opcode.NEGM,
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Opcode.INC,
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Opcode.INCM,
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Opcode.DEC,
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@ -456,7 +458,7 @@ val OpcodesThatSetStatusbitsButNotCarry = arrayOf(
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Opcode.OR,
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Opcode.XORM,
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Opcode.XORR,
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Opcode.XOR
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Opcode.XOR,
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)
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val OpcodesThatDependOnCarry = arrayOf(
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@ -974,8 +974,16 @@ class VirtualMachine(irProgram: IRProgram) {
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private fun InsNEG(i: IRInstruction) {
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when(i.type!!) {
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IRDataType.BYTE -> registers.setUB(i.reg1!!, (-registers.getUB(i.reg1!!).toInt()).toUByte())
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IRDataType.WORD -> registers.setUW(i.reg1!!, (-registers.getUW(i.reg1!!).toInt()).toUShort())
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IRDataType.BYTE -> {
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val value = -registers.getUB(i.reg1!!).toInt()
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registers.setUB(i.reg1!!, value.toUByte())
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statusbitsNZ(value, IRDataType.BYTE)
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}
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IRDataType.WORD -> {
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val value = -registers.getUW(i.reg1!!).toInt()
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registers.setUW(i.reg1!!, value.toUShort())
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statusbitsNZ(value, IRDataType.WORD)
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}
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IRDataType.FLOAT -> registers.setFloat(i.fpReg1!!, -registers.getFloat(i.fpReg1!!))
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}
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nextPc()
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@ -984,8 +992,16 @@ class VirtualMachine(irProgram: IRProgram) {
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private fun InsNEGM(i: IRInstruction) {
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val address = i.address!!
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when(i.type!!) {
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IRDataType.BYTE -> memory.setUB(address, (-memory.getUB(address).toInt()).toUByte())
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IRDataType.WORD -> memory.setUW(address, (-memory.getUW(address).toInt()).toUShort())
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IRDataType.BYTE -> {
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val value = -memory.getUB(address).toInt()
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memory.setUB(address, value.toUByte())
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statusbitsNZ(value, IRDataType.BYTE)
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}
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IRDataType.WORD -> {
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val value = -memory.getUW(address).toInt()
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memory.setUW(address, value.toUShort())
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statusbitsNZ(value, IRDataType.WORD)
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}
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IRDataType.FLOAT -> memory.setFloat(address, -memory.getFloat(address))
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}
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nextPc()
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