mirror of
https://github.com/irmen/prog8.git
synced 2025-02-16 22:30:46 +00:00
more split array stuff for 6502
This commit is contained in:
Irmen de Jong
parent
c94e292176
commit
3ac9036c79
@ -368,7 +368,10 @@ class AsmGen6502Internal (
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val reg = register.toString().lowercase()
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val indexnum = expr.index.asConstInteger()
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if (indexnum != null) {
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val indexValue = indexnum * options.compTarget.memorySize(elementDt) + if (addOneExtra) 1 else 0
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val indexValue = if(expr.splitWords)
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indexnum + if (addOneExtra) 1 else 0
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else
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indexnum * options.compTarget.memorySize(elementDt) + if (addOneExtra) 1 else 0
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out(" ld$reg #$indexValue")
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return
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}
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@ -378,8 +381,23 @@ class AsmGen6502Internal (
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val indexName = asmVariableName(indexVar)
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if(expr.splitWords)
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TODO("split word access ${expr.position}")
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if(expr.splitWords) {
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if(addOneExtra) {
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out(" ldy $indexName | iny")
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when (register) {
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CpuRegister.A -> out(" tya")
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CpuRegister.X -> out(" txy")
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CpuRegister.Y -> {}
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}
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} else {
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when (register) {
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CpuRegister.A -> out(" lda $indexName")
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CpuRegister.X -> out(" ldx $indexName")
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CpuRegister.Y -> out(" ldy $indexName")
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}
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}
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return
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}
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if (addOneExtra) {
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// add 1 to the result
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@ -389,15 +407,13 @@ class AsmGen6502Internal (
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when (register) {
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CpuRegister.A -> out(" tya")
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CpuRegister.X -> out(" tyx")
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CpuRegister.Y -> {
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}
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CpuRegister.Y -> {}
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}
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}
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in WordDatatypes -> {
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out(" lda $indexName | sec | rol a")
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when (register) {
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CpuRegister.A -> {
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}
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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@ -413,8 +429,7 @@ class AsmGen6502Internal (
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adc $indexName"""
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)
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when (register) {
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CpuRegister.A -> {
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}
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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@ -427,8 +442,7 @@ class AsmGen6502Internal (
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in WordDatatypes -> {
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out(" lda $indexName | asl a")
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when (register) {
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CpuRegister.A -> {
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}
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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@ -444,8 +458,7 @@ class AsmGen6502Internal (
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adc $indexName"""
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)
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when (register) {
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CpuRegister.A -> {
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}
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CpuRegister.A -> {}
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CpuRegister.X -> out(" tax")
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CpuRegister.Y -> out(" tay")
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}
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@ -433,7 +433,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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when (what) {
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is PtArrayIndexer -> {
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if(what.splitWords)
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TODO("splitwords ${what.position}")
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TODO("ror2 split words ${what.position}")
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translateRolRorArrayArgs(what.variable, what, "ror2", 'w')
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asmgen.out(" jsr prog8_lib.ror2_array_uw")
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}
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@ -494,7 +494,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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when (what) {
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is PtArrayIndexer -> {
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if(what.splitWords)
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TODO("splitwords ${what.position}")
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TODO("ror split words ${what.position}")
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translateRolRorArrayArgs(what.variable, what, "ror", 'w')
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asmgen.out(" jsr prog8_lib.ror_array_uw")
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}
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@ -538,7 +538,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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when (what) {
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is PtArrayIndexer -> {
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if(what.splitWords)
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TODO("splitwords ${what.position}")
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TODO("rol2 split words ${what.position}")
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translateRolRorArrayArgs(what.variable, what, "rol2", 'w')
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asmgen.out(" jsr prog8_lib.rol2_array_uw")
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}
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@ -599,7 +599,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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when (what) {
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is PtArrayIndexer -> {
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if(what.splitWords)
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TODO("splitwords ${what.position}")
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TODO("rol split words ${what.position}")
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translateRolRorArrayArgs(what.variable, what, "rol", 'w')
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asmgen.out(" jsr prog8_lib.rol_array_uw")
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}
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@ -616,7 +616,7 @@ internal class BuiltinFunctionsAsmGen(private val program: PtProgram,
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private fun translateRolRorArrayArgs(arrayvar: PtIdentifier, indexer: PtArrayIndexer, operation: String, dt: Char) {
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if(indexer.splitWords)
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TODO("split word access ${indexer.position}")
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TODO("rol/ror split words access ${indexer.position}")
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if(arrayvar.type==DataType.UWORD) {
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if(dt!='b')
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throw AssemblyError("non-array var indexing requires bytes dt")
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@ -238,7 +238,7 @@ internal class ExpressionsAsmGen(private val program: PtProgram,
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asmgen.out(" lda #<$varname | ldy #>$varname| jsr floats.push_float")
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}
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in SplitWordArrayTypes -> {
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TODO("split $varname")
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throw AssemblyError("can't push address of split-word array ${expr.position}")
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}
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in IterableDatatypes -> {
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asmgen.out(" lda #<$varname | sta P8ESTACK_LO,x | lda #>$varname | sta P8ESTACK_HI,x | dex")
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@ -748,7 +748,7 @@ internal class ExpressionsAsmGen(private val program: PtProgram,
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val arrayVarName = asmgen.asmVariableName(arrayExpr.variable)
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if(arrayExpr.splitWords)
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TODO("split word access ${arrayExpr.position}")
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TODO("split words ${arrayExpr.position}")
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if(arrayExpr.variable.type==DataType.UWORD) {
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// indexing a pointer var instead of a real array or string
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@ -441,7 +441,7 @@ $loopLabel sty $indexVar
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// allocate index var on ZP if possible
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val result = zeropage.allocate(indexVar, DataType.UBYTE, null, stmt.position, asmgen.errors)
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result.fold(
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success = { (address,_)-> asmgen.out("""$indexVar = $address ; auto zp UBYTE""") },
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success = { (address,_,_)-> asmgen.out("""$indexVar = $address ; auto zp UBYTE""") },
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failure = { asmgen.out("$indexVar .byte 0") }
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)
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} else {
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@ -449,13 +449,44 @@ $loopLabel sty $indexVar
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}
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asmgen.out(endLabel)
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}
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DataType.ARRAY_UW_SPLIT -> {
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asmgen.out("; TODO iterate over split uword array")
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// TODO("iterate over split uword array")
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}
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DataType.ARRAY_W_SPLIT -> {
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asmgen.out("; TODO iterate over split word array")
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// TODO("iterate over split word array")
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DataType.ARRAY_UW_SPLIT, DataType.ARRAY_W_SPLIT -> {
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numElements!!
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val indexVar = asmgen.makeLabel("for_index")
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val loopvarName = asmgen.asmVariableName(stmt.variable)
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asmgen.out("""
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ldy #0
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$loopLabel sty $indexVar
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lda ${iterableName}_lsb,y
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sta $loopvarName
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lda ${iterableName}_msb,y
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sta $loopvarName+1""")
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asmgen.translate(stmt.statements)
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if(numElements<=255u) {
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asmgen.out("""
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ldy $indexVar
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iny
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cpy #$numElements
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beq $endLabel
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bne $loopLabel""")
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} else {
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// length is 256
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asmgen.out("""
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ldy $indexVar
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iny
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bne $loopLabel
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beq $endLabel""")
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}
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if(numElements>=16u) {
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// allocate index var on ZP if possible
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val result = zeropage.allocate(indexVar, DataType.UBYTE, null, stmt.position, asmgen.errors)
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result.fold(
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success = { (address,_,_)-> asmgen.out("""$indexVar = $address ; auto zp UBYTE""") },
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failure = { asmgen.out("$indexVar .byte 0") }
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)
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} else {
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asmgen.out("$indexVar .byte 0")
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}
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asmgen.out(endLabel)
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}
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DataType.ARRAY_F -> {
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throw AssemblyError("for loop with floating point variables is not supported")
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@ -65,6 +65,31 @@ internal class PostIncrDecrAsmGen(private val program: PtProgram, private val as
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val asmArrayvarname = asmgen.asmVariableName(targetArrayIdx.variable)
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val elementDt = targetArrayIdx.type
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val constIndex = targetArrayIdx.index.asConstInteger()
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if(targetArrayIdx.splitWords) {
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if(constIndex!=null) {
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if(incr)
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asmgen.out(" inc ${asmArrayvarname}_lsb+$constIndex | bne + | inc ${asmArrayvarname}_msb+$constIndex |+")
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else
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asmgen.out("""
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lda ${asmArrayvarname}_lsb+$constIndex
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bne +
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dec ${asmArrayvarname}_msb+$constIndex
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+ dec ${asmArrayvarname}_lsb+$constIndex""")
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} else {
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asmgen.saveRegisterLocal(CpuRegister.X, scope!!)
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asmgen.loadScaledArrayIndexIntoRegister(targetArrayIdx, elementDt, CpuRegister.X)
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if(incr)
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asmgen.out(" inc ${asmArrayvarname}_lsb,x | bne + | inc ${asmArrayvarname}_msb,x |+")
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else
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asmgen.out("""
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lda ${asmArrayvarname}_lsb,x
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bne +
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dec ${asmArrayvarname}_msb,x
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+ dec ${asmArrayvarname}_lsb,x""")
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asmgen.restoreRegisterLocal(CpuRegister.X)
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}
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return
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}
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if(constIndex!=null) {
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val indexValue = constIndex * program.memsizer.memorySize(elementDt)
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when(elementDt) {
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@ -74,11 +99,10 @@ internal class PostIncrDecrAsmGen(private val program: PtProgram, private val as
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asmgen.out(" inc $asmArrayvarname+$indexValue | bne + | inc $asmArrayvarname+$indexValue+1 |+")
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else
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asmgen.out("""
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lda $asmArrayvarname+$indexValue
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bne +
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dec $asmArrayvarname+$indexValue+1
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+ dec $asmArrayvarname+$indexValue
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""")
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lda $asmArrayvarname+$indexValue
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bne +
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dec $asmArrayvarname+$indexValue+1
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+ dec $asmArrayvarname+$indexValue""")
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}
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DataType.FLOAT -> {
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asmgen.out(" lda #<($asmArrayvarname+$indexValue) | ldy #>($asmArrayvarname+$indexValue)")
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@ -89,9 +113,8 @@ internal class PostIncrDecrAsmGen(private val program: PtProgram, private val as
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}
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else
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{
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asmgen.loadScaledArrayIndexIntoRegister(targetArrayIdx, elementDt, CpuRegister.A)
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asmgen.saveRegisterLocal(CpuRegister.X, scope!!)
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asmgen.out(" tax")
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asmgen.loadScaledArrayIndexIntoRegister(targetArrayIdx, elementDt, CpuRegister.X)
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when(elementDt) {
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in ByteDatatypes -> {
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asmgen.out(if(incr) " inc $asmArrayvarname,x" else " dec $asmArrayvarname,x")
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@ -101,20 +124,20 @@ internal class PostIncrDecrAsmGen(private val program: PtProgram, private val as
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asmgen.out(" inc $asmArrayvarname,x | bne + | inc $asmArrayvarname+1,x |+")
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else
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asmgen.out("""
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lda $asmArrayvarname,x
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bne +
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dec $asmArrayvarname+1,x
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lda $asmArrayvarname,x
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bne +
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dec $asmArrayvarname+1,x
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+ dec $asmArrayvarname,x
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""")
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}
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DataType.FLOAT -> {
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asmgen.out("""
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ldy #>$asmArrayvarname
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clc
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adc #<$asmArrayvarname
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bcc +
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iny
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+ jsr floats.inc_var_f""")
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ldy #>$asmArrayvarname
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clc
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adc #<$asmArrayvarname
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bcc +
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iny
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+ jsr floats.inc_var_f""")
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}
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else -> throw AssemblyError("weird array elt dt")
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}
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@ -629,11 +629,15 @@ internal class ProgramAndVarsGen(
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}
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DataType.ARRAY_UW_SPLIT -> {
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val data = makeArrayFillDataUnsigned(dt, value, orNumberOfZeros)
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// TODO("gen split uword array $data")
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asmgen.out("_array_$varname := ${data.joinToString()}")
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asmgen.out("${varname}_lsb\t.byte <_array_$varname")
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asmgen.out("${varname}_msb\t.byte >_array_$varname")
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}
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DataType.ARRAY_W_SPLIT -> {
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val data = makeArrayFillDataSigned(dt, value, orNumberOfZeros)
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// TODO("gen split word array $data")
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asmgen.out("_array_$varname := ${data.joinToString()}")
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asmgen.out("${varname}_lsb\t.byte <_array_$varname")
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asmgen.out("${varname}_msb\t.byte >_array_$varname")
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}
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DataType.ARRAY_F -> {
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val array = value ?: zeroFilledArray(orNumberOfZeros!!)
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@ -730,7 +734,7 @@ internal class ProgramAndVarsGen(
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val number = it.number!!.toInt()
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"$" + number.toString(16).padStart(4, '0')
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}
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in SplitWordArrayTypes -> array.map {
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DataType.ARRAY_W, DataType.ARRAY_W_SPLIT -> array.map {
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val number = it.number!!.toInt()
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val hexnum = number.absoluteValue.toString(16).padStart(4, '0')
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if(number>=0)
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@ -172,8 +172,6 @@ internal class AsmAssignSource(val kind: SourceStorageKind,
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AsmAssignSource(SourceStorageKind.MEMORY, program, asmgen, DataType.UBYTE, memory = value)
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}
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is PtArrayIndexer -> {
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if(value.splitWords)
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TODO("splitwords ${value.position}")
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AsmAssignSource(SourceStorageKind.ARRAY, program, asmgen, value.type, array = value)
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}
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is PtBuiltinFunctionCall -> {
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@ -80,6 +80,20 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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val constIndex = value.index.asConstInteger()
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if(value.splitWords) {
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require(elementDt in WordDatatypes)
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if(constIndex!=null) {
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asmgen.out(" lda ${arrayVarName}_lsb+$constIndex | ldy ${arrayVarName}_msb+$constIndex")
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assignRegisterpairWord(assign.target, RegisterOrPair.AY)
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} else {
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asmgen.loadScaledArrayIndexIntoRegister(value, elementDt, CpuRegister.Y)
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asmgen.out(" lda ${arrayVarName}_lsb,y | pha | lda ${arrayVarName}_msb,y | tay | pla")
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assignRegisterpairWord(assign.target, RegisterOrPair.AY)
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}
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return
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}
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if (constIndex!=null) {
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// constant array index value
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val indexValue = constIndex * program.memsizer.memorySize(elementDt)
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@ -1455,6 +1469,8 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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// return
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// }
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TargetStorageKind.ARRAY -> {
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if(target.array!!.splitWords)
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TODO("assign type casted byte into split words ${target.position}")
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// byte to word, just assign to registers first, then assign into array
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assignExpressionToRegister(value, RegisterOrPair.AY, targetDt==DataType.WORD)
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assignRegisterpairWord(target, RegisterOrPair.AY)
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@ -1851,6 +1867,8 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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asmgen.out(" inx | lda P8ESTACK_LO,x | sta ${target.asmVarname}+$scaledIdx")
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}
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in WordDatatypes -> {
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if(target.array!!.splitWords)
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TODO("assign word stack value into split words ${target.position}")
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asmgen.out("""
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inx
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lda P8ESTACK_LO,x
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@ -2054,6 +2072,8 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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TargetStorageKind.ARRAY -> {
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target.array!!
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if(target.array.splitWords)
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TODO("assign var into split words ${target.position}")
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if(target.constArrayIndexValue!=null) {
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val scaledIdx = target.constArrayIndexValue!! * program.memsizer.memorySize(target.datatype).toUInt()
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when(target.datatype) {
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@ -2348,6 +2368,8 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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""")
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}
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TargetStorageKind.ARRAY -> {
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if(wordtarget.array!!.splitWords)
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TODO("assign byte into split words ${wordtarget.position}")
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if (wordtarget.constArrayIndexValue!=null) {
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val scaledIdx = wordtarget.constArrayIndexValue!! * 2u
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asmgen.out(" lda $sourceName")
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@ -2356,7 +2378,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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else {
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asmgen.saveRegisterLocal(CpuRegister.X, wordtarget.scope!!)
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asmgen.loadScaledArrayIndexIntoRegister(wordtarget.array!!, wordtarget.datatype, CpuRegister.X)
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asmgen.loadScaledArrayIndexIntoRegister(wordtarget.array, wordtarget.datatype, CpuRegister.X)
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asmgen.out(" lda $sourceName")
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asmgen.signExtendAYlsb(DataType.BYTE)
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asmgen.out(" sta ${wordtarget.asmVarname},x | inx | tya | sta ${wordtarget.asmVarname},x")
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@ -2698,6 +2720,8 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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}
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TargetStorageKind.ARRAY -> {
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if(target.array!!.splitWords)
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TODO("assign register pair into split words ${target.position}")
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if (target.constArrayIndexValue!=null) {
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val idx = target.constArrayIndexValue!! * 2u
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when (regs) {
|
||||
@ -2723,7 +2747,7 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
RegisterOrPair.XY -> asmgen.out(" txa | pha | tya | pha")
|
||||
else -> throw AssemblyError("expected reg pair")
|
||||
}
|
||||
asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UWORD, CpuRegister.Y, true)
|
||||
asmgen.loadScaledArrayIndexIntoRegister(target.array, DataType.UWORD, CpuRegister.Y, true)
|
||||
asmgen.out("""
|
||||
pla
|
||||
sta ${target.asmVarname},y
|
||||
@ -2833,11 +2857,16 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
TargetStorageKind.ARRAY -> {
|
||||
asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UWORD, CpuRegister.Y)
|
||||
asmgen.out("""
|
||||
lda #0
|
||||
sta ${target.asmVarname},y
|
||||
sta ${target.asmVarname}+1,y
|
||||
""")
|
||||
if(target.array.splitWords)
|
||||
asmgen.out("""
|
||||
lda #0
|
||||
sta ${target.asmVarname}_lsb,y
|
||||
sta ${target.asmVarname}_msb,y""")
|
||||
else
|
||||
asmgen.out("""
|
||||
lda #0
|
||||
sta ${target.asmVarname},y
|
||||
sta ${target.asmVarname}+1,y""")
|
||||
}
|
||||
TargetStorageKind.REGISTER -> {
|
||||
when(target.register!!) {
|
||||
@ -2885,12 +2914,18 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
}
|
||||
TargetStorageKind.ARRAY -> {
|
||||
asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UWORD, CpuRegister.Y)
|
||||
asmgen.out("""
|
||||
lda #<${word.toHex()}
|
||||
sta ${target.asmVarname},y
|
||||
lda #>${word.toHex()}
|
||||
sta ${target.asmVarname}+1,y
|
||||
""")
|
||||
if(target.array.splitWords)
|
||||
asmgen.out("""
|
||||
lda #<${word.toHex()}
|
||||
sta ${target.asmVarname}_lsb,y
|
||||
lda #>${word.toHex()}
|
||||
sta ${target.asmVarname}_msb,y""")
|
||||
else
|
||||
asmgen.out("""
|
||||
lda #<${word.toHex()}
|
||||
sta ${target.asmVarname},y
|
||||
lda #>${word.toHex()}
|
||||
sta ${target.asmVarname}+1,y""")
|
||||
}
|
||||
TargetStorageKind.REGISTER -> {
|
||||
when(target.register!!) {
|
||||
@ -3272,6 +3307,8 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
asmgen.out(" lda #0 | sta ${wordtarget.asmVarname}+1")
|
||||
}
|
||||
TargetStorageKind.ARRAY -> {
|
||||
if(wordtarget.array!!.splitWords)
|
||||
TODO("assign mem byte into split words ${wordtarget.position}")
|
||||
asmgen.out(" lda ${address.toHex()} | ldy #0")
|
||||
assignRegisterpairWord(wordtarget, RegisterOrPair.AY)
|
||||
}
|
||||
@ -3301,6 +3338,8 @@ internal class AssignmentAsmGen(private val program: PtProgram,
|
||||
asmgen.out(" lda #0 | sta ${wordtarget.asmVarname}+1")
|
||||
}
|
||||
TargetStorageKind.ARRAY -> {
|
||||
if(wordtarget.array!!.splitWords)
|
||||
TODO("assign mem byte into split words ${wordtarget.position}")
|
||||
asmgen.loadByteFromPointerIntoA(identifier)
|
||||
asmgen.out(" ldy #0")
|
||||
assignRegisterpairWord(wordtarget, RegisterOrPair.AY)
|
||||
|
||||
@ -193,6 +193,8 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
|
||||
TargetStorageKind.ARRAY -> {
|
||||
val indexNum = target.array!!.index as? PtNumber
|
||||
val indexVar = target.array.index as? PtIdentifier
|
||||
if(target.array.splitWords)
|
||||
TODO("in-place assign split words ${target.position}")
|
||||
when {
|
||||
indexNum!=null -> {
|
||||
val targetVarName = "${target.asmVarname} + ${indexNum.number.toInt()*program.memsizer.memorySize(target.datatype)}"
|
||||
|
||||
@ -1369,20 +1369,20 @@ class IRCodeGen(
|
||||
private fun translate(postIncrDecr: PtPostIncrDecr): IRCodeChunks {
|
||||
val operationMem: Opcode
|
||||
val operationRegister: Opcode
|
||||
val array = postIncrDecr.target.array
|
||||
when(postIncrDecr.operator) {
|
||||
"++" -> {
|
||||
operationMem = Opcode.INCM
|
||||
operationMem = if(array?.splitWords==true) Opcode.INCMSPLIT else Opcode.INCM
|
||||
operationRegister = Opcode.INC
|
||||
}
|
||||
"--" -> {
|
||||
operationMem = Opcode.DECM
|
||||
operationMem = if(array?.splitWords==true) Opcode.DECMSPLIT else Opcode.DECM
|
||||
operationRegister = Opcode.DEC
|
||||
}
|
||||
else -> throw AssemblyError("weird operator")
|
||||
}
|
||||
val ident = postIncrDecr.target.identifier
|
||||
val memory = postIncrDecr.target.memory
|
||||
val array = postIncrDecr.target.array
|
||||
val irDt = irType(postIncrDecr.target.type)
|
||||
val result = mutableListOf<IRCodeChunkBase>()
|
||||
if(ident!=null) {
|
||||
@ -1405,18 +1405,35 @@ class IRCodeGen(
|
||||
val variable = array.variable.name
|
||||
val itemsize = program.memsizer.memorySize(array.type)
|
||||
val fixedIndex = constIntValue(array.index)
|
||||
if(fixedIndex!=null) {
|
||||
val offset = fixedIndex*itemsize
|
||||
addInstr(result, IRInstruction(operationMem, irDt, labelSymbol="$variable+$offset"), null)
|
||||
if(array.splitWords) {
|
||||
val iterable = symbolTable.flat.getValue(array.variable.name) as StStaticVariable
|
||||
val arrayLength = iterable.length!!
|
||||
if(fixedIndex!=null) {
|
||||
addInstr(result, IRInstruction(operationMem, irDt, immediate = arrayLength, labelSymbol="$variable+$fixedIndex"), null)
|
||||
} else {
|
||||
val indexTr = expressionEval.translateExpression(array.index)
|
||||
addToResult(result, indexTr, indexTr.resultReg, -1)
|
||||
val chunk = IRCodeChunk(null, null)
|
||||
val incReg = registers.nextFree()
|
||||
chunk += IRInstruction(Opcode.LOADXSPLIT, irDt, reg1=incReg, reg2=indexTr.resultReg, immediate = arrayLength, labelSymbol=variable)
|
||||
chunk += IRInstruction(operationRegister, irDt, reg1=incReg)
|
||||
chunk += IRInstruction(Opcode.STOREXSPLIT, irDt, reg1=incReg, reg2=indexTr.resultReg, immediate = arrayLength, labelSymbol=variable)
|
||||
result += chunk
|
||||
}
|
||||
} else {
|
||||
val indexTr = expressionEval.translateExpression(array.index)
|
||||
addToResult(result, indexTr, indexTr.resultReg, -1)
|
||||
val chunk = IRCodeChunk(null, null)
|
||||
val incReg = registers.nextFree()
|
||||
chunk += IRInstruction(Opcode.LOADX, irDt, reg1=incReg, reg2=indexTr.resultReg, labelSymbol=variable)
|
||||
chunk += IRInstruction(operationRegister, irDt, reg1=incReg)
|
||||
chunk += IRInstruction(Opcode.STOREX, irDt, reg1=incReg, reg2=indexTr.resultReg, labelSymbol=variable)
|
||||
result += chunk
|
||||
if(fixedIndex!=null) {
|
||||
val offset = fixedIndex*itemsize
|
||||
addInstr(result, IRInstruction(operationMem, irDt, labelSymbol="$variable+$offset"), null)
|
||||
} else {
|
||||
val indexTr = expressionEval.translateExpression(array.index)
|
||||
addToResult(result, indexTr, indexTr.resultReg, -1)
|
||||
val chunk = IRCodeChunk(null, null)
|
||||
val incReg = registers.nextFree()
|
||||
chunk += IRInstruction(Opcode.LOADX, irDt, reg1=incReg, reg2=indexTr.resultReg, labelSymbol=variable)
|
||||
chunk += IRInstruction(operationRegister, irDt, reg1=incReg)
|
||||
chunk += IRInstruction(Opcode.STOREX, irDt, reg1=incReg, reg2=indexTr.resultReg, labelSymbol=variable)
|
||||
result += chunk
|
||||
}
|
||||
}
|
||||
} else
|
||||
throw AssemblyError("weird assigntarget")
|
||||
|
||||
@ -74,7 +74,12 @@ main {
|
||||
txt.nl()
|
||||
|
||||
split_uwords[1]++
|
||||
split_words[1]--
|
||||
split_words[1]++
|
||||
|
||||
print_arrays()
|
||||
txt.nl()
|
||||
split_uwords[1] |= 4095
|
||||
split_words[1] |= 127
|
||||
|
||||
print_arrays()
|
||||
txt.nl()
|
||||
|
||||
@ -121,8 +121,10 @@ exts reg1 - reg1 = signed extension of reg1 (b
|
||||
ext reg1 - reg1 = unsigned extension of reg1 (which in practice just means clearing the MSB / MSW) (ext.w not yet implemented as we don't have longs yet)
|
||||
inc reg1 - reg1 = reg1+1
|
||||
incm address - memory at address += 1
|
||||
incmsplit arraylen, address - memory at address += 1 (in lsb/msb split word array)
|
||||
dec reg1 - reg1 = reg1-1
|
||||
decm address - memory at address -= 1
|
||||
decmsplit arraylen, address - memory at address -= 1 (in lsb/msb split word array)
|
||||
neg reg1 - reg1 = sign negation of reg1
|
||||
negm address - sign negate memory at address
|
||||
addr reg1, reg2 - reg1 += reg2
|
||||
@ -293,8 +295,10 @@ enum class Opcode {
|
||||
|
||||
INC,
|
||||
INCM,
|
||||
INCMSPLIT,
|
||||
DEC,
|
||||
DECM,
|
||||
DECMSPLIT,
|
||||
NEG,
|
||||
NEGM,
|
||||
ADDR,
|
||||
@ -571,8 +575,10 @@ val instructionFormats = mutableMapOf(
|
||||
Opcode.SGES to InstructionFormat.from("BW,<>r1,<r2"),
|
||||
Opcode.INC to InstructionFormat.from("BW,<>r1 | F,<>fr1"),
|
||||
Opcode.INCM to InstructionFormat.from("BW,<>a | F,<>a"),
|
||||
Opcode.INCMSPLIT to InstructionFormat.from("W,<i,<>a"),
|
||||
Opcode.DEC to InstructionFormat.from("BW,<>r1 | F,<>fr1"),
|
||||
Opcode.DECM to InstructionFormat.from("BW,<>a | F,<>a"),
|
||||
Opcode.DECMSPLIT to InstructionFormat.from("W,<i,<>a"),
|
||||
Opcode.NEG to InstructionFormat.from("BW,<>r1 | F,<>fr1"),
|
||||
Opcode.NEGM to InstructionFormat.from("BW,<>a | F,<>a"),
|
||||
Opcode.ADDR to InstructionFormat.from("BW,<>r1,<r2 | F,<>fr1,<fr2"),
|
||||
|
||||
@ -13,11 +13,11 @@
|
||||
</options>
|
||||
<keywords keywords="&;->;@;and;as;asmsub;break;clobbers;do;downto;else;false;for;goto;if;if_cc;if_cs;if_eq;if_mi;if_ne;if_neg;if_nz;if_pl;if_pos;if_vc;if_vs;if_z;in;inline;not;or;repeat;return;romsub;step;sub;to;true;unroll;until;when;while;xor;~" ignore_case="false" />
|
||||
<keywords2 keywords="%address;%asm;%asmbinary;%asminclude;%breakpoint;%import;%ir;%launcher;%option;%output;%zeropage;%zpreserved;iso:;petscii:;sc:" />
|
||||
<keywords3 keywords="@requirezp;@shared;@zp;bool;byte;const;float;str;ubyte;uword;void;word" />
|
||||
<keywords3 keywords="@requirezp;@shared;@split;@zp;bool;byte;const;float;str;ubyte;uword;void;word" />
|
||||
<keywords4 keywords="abs;all;any;callfar;callram;callrom;clamp;cmp;divmod;len;lsb;max;memory;min;mkword;msb;peek;peekw;poke;pokew;pop;popw;push;pushw;reverse;rol;rol2;ror;ror2;rrestore;rrestorex;rsave;rsavex;sgn;sizeof;sort;sqrt;sqrt16;swap;|>" />
|
||||
</highlighting>
|
||||
<extensionMap>
|
||||
<mapping ext="p8" />
|
||||
<mapping ext="prog8" />
|
||||
</extensionMap>
|
||||
</filetype>
|
||||
</filetype>
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
<Keywords name="Folders in comment, open"></Keywords>
|
||||
<Keywords name="Folders in comment, middle"></Keywords>
|
||||
<Keywords name="Folders in comment, close"></Keywords>
|
||||
<Keywords name="Keywords1">void const
str
byte ubyte bool
word uword
float
zp shared requirezp</Keywords>
|
||||
<Keywords name="Keywords1">void const
str
byte ubyte bool
word uword
float
zp shared split requirezp</Keywords>
|
||||
<Keywords name="Keywords2">%address
%asm
%ir
%asmbinary
%asminclude
%breakpoint
%import
%launcher
%option
%output
%zeropage
%zpreserved</Keywords>
|
||||
<Keywords name="Keywords3">inline sub asmsub romsub
clobbers
asm
if
when else
if_cc if_cs if_eq if_mi if_neg if_nz if_pl if_pos if_vc if_vs if_z
for in step do while repeat unroll
break return goto</Keywords>
|
||||
<Keywords name="Keywords4">abs all any callfar clamp cmp divmod len lsb lsl lsr memory mkword min max msb peek peekw poke pokew push pushw pop popw rsave rsavex rrestore rrestorex reverse rnd rndw rol rol2 ror ror2 sgn sizeof sort sqrtw swap</Keywords>
|
||||
|
||||
@ -43,7 +43,7 @@ syn region prog8ArrayType matchgroup=prog8Type
|
||||
\ start="\<\%(u\?byte\|u\?word\|float\|str\|bool\)\[" end="\]"
|
||||
\ transparent
|
||||
syn keyword prog8StorageClass const
|
||||
syn match prog8StorageClass "\(^\|\s\)\(@zp\|@shared\|@requirezp\)\>"
|
||||
syn match prog8StorageClass "\(^\|\s\)\(@zp\|@shared\|@split\|@requirezp\)\>"
|
||||
|
||||
syn region prog8Block start="{" end="}" transparent
|
||||
syn region prog8Expression start="(" end=")" transparent
|
||||
|
||||
@ -223,8 +223,10 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
Opcode.SGES -> InsSGES(ins)
|
||||
Opcode.INC -> InsINC(ins)
|
||||
Opcode.INCM -> InsINCM(ins)
|
||||
Opcode.INCMSPLIT -> InsINCMSPLIT(ins)
|
||||
Opcode.DEC -> InsDEC(ins)
|
||||
Opcode.DECM -> InsDECM(ins)
|
||||
Opcode.DECMSPLIT -> InsDECMSPLIT(ins)
|
||||
Opcode.NEG -> InsNEG(ins)
|
||||
Opcode.NEGM -> InsNEGM(ins)
|
||||
Opcode.ADDR -> InsADDR(ins)
|
||||
@ -919,6 +921,20 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsINCMSPLIT(i: IRInstruction) {
|
||||
val address = i.address!!
|
||||
var lsb = memory.getUB(address).toInt()
|
||||
var msb = memory.getUB(address+i.immediate!!).toInt()
|
||||
lsb++
|
||||
if(lsb>255) {
|
||||
lsb = 0
|
||||
msb++
|
||||
}
|
||||
memory.setUB(address, lsb.toUByte())
|
||||
memory.setUB(address+i.immediate!!, msb.toUByte())
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsDEC(i: IRInstruction) {
|
||||
when(i.type!!) {
|
||||
IRDataType.BYTE -> registers.setUB(i.reg1!!, (registers.getUB(i.reg1!!)-1u).toUByte())
|
||||
@ -937,6 +953,21 @@ class VirtualMachine(irProgram: IRProgram) {
|
||||
nextPc()
|
||||
}
|
||||
|
||||
private fun InsDECMSPLIT(i: IRInstruction) {
|
||||
val address = i.address!!
|
||||
var lsb = memory.getUB(address).toInt()
|
||||
var msb = memory.getUB(address+i.immediate!!).toInt()
|
||||
lsb--
|
||||
if(lsb<0) {
|
||||
lsb = 255
|
||||
msb--
|
||||
}
|
||||
memory.setUB(address, lsb.toUByte())
|
||||
memory.setUB(address+i.immediate!!, msb.toUByte())
|
||||
nextPc()
|
||||
|
||||
}
|
||||
|
||||
private fun InsNEG(i: IRInstruction) {
|
||||
when(i.type!!) {
|
||||
IRDataType.BYTE -> registers.setUB(i.reg1!!, (-registers.getUB(i.reg1!!).toInt()).toUByte())
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user