mirror of
https://github.com/irmen/prog8.git
synced 2024-06-25 15:29:45 +00:00
fix vm signed comparisons
This commit is contained in:
Irmen de Jong
parent
f07065bf84
commit
3e1a7c6102
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@ -92,6 +92,13 @@ internal class BuiltinFuncGen(val codeGen: CodeGen, val exprGen: ExpressionGen)
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code += exprGen.translateExpression(call.args.single(), addressReg, regUsage)
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code += VmCodeInstruction(Instruction(Opcode.LOADI, VmDataType.WORD, reg1 = resultRegister, reg2=addressReg))
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}
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"mkword" -> {
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val msbReg = regUsage.nextFree()
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val lsbReg = regUsage.nextFree()
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code += exprGen.translateExpression(call.args[0], msbReg, regUsage)
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code += exprGen.translateExpression(call.args[1], lsbReg, regUsage)
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code += VmCodeInstruction(Instruction(Opcode.CONCAT, VmDataType.BYTE, reg1=resultRegister, reg2=msbReg, reg3=lsbReg))
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}
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else -> {
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TODO("builtinfunc ${call.name}")
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// code += VmCodeInstruction(Instruction(Opcode.NOP))
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@ -233,7 +233,8 @@ internal class ExpressionGen(val codeGen: CodeGen) {
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val rightCode = translateExpression(binExpr.right, rightResultReg, regUsage)
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code += leftCode
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code += rightCode
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val vmDt = codeGen.vmType(binExpr.type)
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val vmDt = codeGen.vmType(binExpr.left.type)
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val signed = binExpr.left.type in SignedDatatypes
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when(binExpr.operator) {
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"+" -> {
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code += VmCodeInstruction(Instruction(Opcode.ADD, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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@ -263,7 +264,8 @@ internal class ExpressionGen(val codeGen: CodeGen) {
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code += VmCodeInstruction(Instruction(Opcode.LSL, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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}
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">>" -> {
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code += VmCodeInstruction(Instruction(Opcode.LSR, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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val opc = if(signed) Opcode.ASR else Opcode.LSR
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code += VmCodeInstruction(Instruction(opc, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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}
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"==" -> {
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code += VmCodeInstruction(Instruction(Opcode.SEQ, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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@ -272,19 +274,19 @@ internal class ExpressionGen(val codeGen: CodeGen) {
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code += VmCodeInstruction(Instruction(Opcode.SNE, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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}
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"<" -> {
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val ins = if(binExpr.type in SignedDatatypes) Opcode.SLTS else Opcode.SLT
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val ins = if(signed) Opcode.SLTS else Opcode.SLT
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code += VmCodeInstruction(Instruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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}
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">" -> {
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val ins = if(binExpr.type in SignedDatatypes) Opcode.SGTS else Opcode.SGT
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val ins = if(signed) Opcode.SGTS else Opcode.SGT
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code += VmCodeInstruction(Instruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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}
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"<=" -> {
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val ins = if(binExpr.type in SignedDatatypes) Opcode.SLES else Opcode.SLE
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val ins = if(signed) Opcode.SLES else Opcode.SLE
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code += VmCodeInstruction(Instruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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}
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">=" -> {
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val ins = if(binExpr.type in SignedDatatypes) Opcode.SGES else Opcode.SGE
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val ins = if(signed) Opcode.SGES else Opcode.SGE
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code += VmCodeInstruction(Instruction(ins, vmDt, reg1=resultRegister, reg2=leftResultReg, reg3=rightResultReg))
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}
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else -> throw AssemblyError("weird operator ${binExpr.operator}")
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@ -32,6 +32,9 @@ sys {
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const ubyte SC_GFX_ENABLE = 8
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const ubyte SC_GFX_CLEAR = 9
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const ubyte SC_GFX_PLOT = 10
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const ubyte SC_RND = 11
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const ubyte SC_WAIT = 12
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const ubyte SC_WAITVSYNC = 13
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sub reset_system() {
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@ -41,24 +44,34 @@ sys {
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sub wait(uword jiffies) {
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; --- wait approximately the given number of jiffies (1/60th seconds)
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; TODO
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syscall1(SC_WAIT, jiffies)
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}
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sub waitvsync() {
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; --- busy wait till the next vsync has occurred (approximately), without depending on custom irq handling.
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; TODO
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syscall(SC_WAITVSYNC)
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}
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sub memcopy(uword source, uword target, uword count) {
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; TODO
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repeat count {
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@(target) = @(source)
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source++
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target++
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}
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}
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sub memset(uword mem, uword numbytes, ubyte value) {
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; TODO
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repeat numbytes {
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@(mem) = value
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mem++
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}
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}
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sub memsetw(uword mem, uword numwords, uword value) {
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; TODO
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repeat numwords {
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pokew(mem, value)
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mem+=2
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}
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}
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sub exit(ubyte returnvalue) {
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@ -3,7 +3,6 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- vm codegen: fix ifelse comparisons such as if x< 0
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- vm codegen: fix primes endless loop stuck on '2'
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- x16: check additional FP lib changes https://github.com/commanderx16/x16-rom/commit/ae608673f0210953172d6837acfbb231d62ddbd1
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and https://github.com/commanderx16/x16-docs/commit/21238aedc641da91df88e04c4ce9bf3324a3c12d
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@ -13,6 +12,7 @@ For next release
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broken examples: amiga, colorbars, cube3d, highresbitmap, rasterbars, tehtriz, testgfx2, testvtui
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can we make the code read the new layout from vera registers instead of hardcoding it?
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- x16: check new ZP free addresses https://github.com/commanderx16/x16-docs/commit/541f2ce9e61d1d0d0e157d7f52fe16bc0895e6f0
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and https://www.commanderx16.com/forum/index.php?/topic/363-keep-zero-page-empty-as-much-as-possible/#comment-18561
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- x16: optimize diskio load_raw because headerless files are now supported https://github.com/commanderx16/x16-rom/pull/216
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note: must still work on c64/c128 that don't have this!
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- major compiler version bump once X16 r39 rom is officially finalized
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@ -23,6 +23,7 @@ For next release
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- vm codegen: postincrdecr arrayvalue
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- vm: support no globals re-init option
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- vm: how to remove all unused subroutines? (for asm, 64tass used to do this)
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- vm: rather than being able to jump to any 'address' (IPTR), use 'blocks'
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- vm codegen/assembler: variable memory locations should also be referenced by the variable name instead of just the address
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- when the vm is stable and *if* its language can get promoted to prog8 IL, the variable allocation should be changed.
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It's now done before the vm code generation, but the IL should probably not depend on the allocations already performed.
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@ -4,39 +4,13 @@
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main {
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sub start() {
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byte bb = -9
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word ww = -1234
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if bb<0 {
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txt.print("bb <0!\n")
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} else {
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txt.print("comparison error!\n")
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}
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if ww<0 {
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txt.print("ww <0!\n")
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} else {
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txt.print("comparison error!\n")
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}
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if bb>0 {
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txt.print("comparison error!\n")
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} else {
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txt.print("bb not >0\n")
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}
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if ww>0 {
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txt.print("comparison error!\n")
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} else {
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txt.print("ww not >0\n")
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}
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txt.print_w(ww)
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txt.spc()
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ww <<= 3
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txt.print_w(ww)
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ubyte x1 = $ea
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ubyte x2 = $31
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uword uw = mkword(x1, $99)
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txt.print_uwhex(uw, true)
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txt.nl()
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txt.print_b(bb)
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txt.spc()
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bb <<= 3
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txt.print_b(bb)
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uw = mkword(x1, x2)
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txt.print_uwhex(uw, true)
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txt.nl()
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sys.exit(99)
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@ -80,6 +54,7 @@ main {
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; sys.exit(99)
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; the "pixelshader":
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; syscall1(8, 0) ; enable lo res creen
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; ubyte shifter
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;
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@ -32,14 +32,14 @@ class Assembler {
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"ubyte", "byte" -> {
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val array = values.split(',').map { parseValue(it.trim(), 0) }
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for (value in array) {
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memory.setB(address, value.toUByte())
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memory.setUB(address, value.toUByte())
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address++
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}
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}
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"uword", "word" -> {
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val array = values.split(',').map { parseValue(it.trim(), 0) }
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for (value in array) {
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memory.setW(address, value.toUShort())
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memory.setUW(address, value.toUShort())
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address++
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}
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}
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@ -115,11 +115,11 @@ and reg1, reg2, reg3 - reg1 = reg2 bitwise and reg3
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or reg1, reg2, reg3 - reg1 = reg2 bitwise or reg3
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xor reg1, reg2, reg3 - reg1 = reg2 bitwise xor reg3
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lsr reg1, reg2, reg3 - reg1 = shift reg2 right by reg3 bits
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asr reg1, reg2, reg3 - reg1 = shift reg2 right by reg3 bits (signed)
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lsl reg1, reg2, reg3 - reg1 = shift reg2 left by reg3 bits
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ror reg1, reg2, reg3 - reg1 = rotate reg2 right by reg3 bits, not using carry
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rol reg1, reg2, reg3 - reg1 = rotate reg2 left by reg3 bits, not using carry
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TODO add asr? (arithmetical shift right, so with sign bit)
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TODO also add ror/rol variants using the carry bit? These do map directly on 6502 and 68k instructions.
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@ -131,6 +131,7 @@ breakpoint - trigger a breakpoint
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copy reg1, reg2, length - copy memory from ptrs in reg1 to reg3, length bytes
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copyz reg1, reg2 - copy memory from ptrs in reg1 to reg3, stop after first 0-byte
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swap [b, w] reg1, reg2 - reg1 = swapped lsb and msb from register reg2 (16 bits) or lsw and msw (32 bits)
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concat [b, w] reg1, reg2, reg3 - reg1 = concatenated lsb/lsw of reg2 and lsb/lsw of reg3 into new word or int (int not yet implemented, requires 32bits regs)
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push [b, w] reg1 - push value in reg1 on the stack
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pop [b, w] reg1 - pop value from stack into reg1
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@ -143,7 +144,6 @@ enum class Opcode {
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LOADI,
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LOADX,
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LOADR,
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SWAPREG,
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STOREM,
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STOREI,
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STOREX,
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@ -194,6 +194,7 @@ enum class Opcode {
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AND,
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OR,
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XOR,
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ASR,
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LSR,
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LSL,
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ROR,
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@ -202,6 +203,8 @@ enum class Opcode {
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PUSH,
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POP,
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SWAP,
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SWAPREG,
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CONCAT,
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COPY,
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COPYZ,
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BREAKPOINT
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@ -321,6 +324,7 @@ val instructionFormats = mutableMapOf(
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Opcode.AND to InstructionFormat(BW, true, true, true, false),
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Opcode.OR to InstructionFormat(BW, true, true, true, false),
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Opcode.XOR to InstructionFormat(BW, true, true, true, false),
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Opcode.ASR to InstructionFormat(BW, true, true, true, false),
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Opcode.LSR to InstructionFormat(BW, true, true, true, false),
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Opcode.LSL to InstructionFormat(BW, true, true, true, false),
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Opcode.ROR to InstructionFormat(BW, true, true, true, false),
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@ -331,5 +335,6 @@ val instructionFormats = mutableMapOf(
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Opcode.SWAP to InstructionFormat(BW, true, true, false, false),
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Opcode.PUSH to InstructionFormat(BW, true, false, false, false),
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Opcode.POP to InstructionFormat(BW, true, false, false, false),
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Opcode.CONCAT to InstructionFormat(BW, true, true, true, false),
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Opcode.BREAKPOINT to InstructionFormat(NN, false, false, false, false)
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)
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@ -10,23 +10,41 @@ class Memory {
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mem.fill(0u)
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}
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fun getB(address: Int): UByte {
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fun getUB(address: Int): UByte {
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return mem[address]
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}
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fun setB(address: Int, value: UByte) {
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fun getSB(address: Int): Byte {
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return mem[address].toByte()
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}
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fun setUB(address: Int, value: UByte) {
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mem[address] = value
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}
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fun getW(address: Int): UShort {
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fun setSB(address: Int, value: Byte) {
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mem[address] = value.toUByte()
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}
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fun getUW(address: Int): UShort {
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return (256u*mem[address] + mem[address+1]).toUShort()
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}
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fun setW(address: Int, value: UShort) {
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fun getSW(address: Int): Short {
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return (mem[address].toInt()*256 + mem[address+1].toInt()).toShort()
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}
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fun setUW(address: Int, value: UShort) {
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mem[address] = (value.toInt() ushr 8).toUByte()
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mem[address+1] = value.toUByte()
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}
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fun setSW(address: Int, value: Short) {
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val uv = value.toUShort()
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mem[address] = (uv.toInt() ushr 8).toUByte()
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mem[address+1] = uv.toUByte()
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}
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// for now, no LONG 32-bits and no FLOAT support.
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// fun getL(address: Int): UInt {
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// return mem[address+3] + 256u*mem[address+2] + 65536u*mem[address+1] + 16777216u*mem[address]
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@ -10,15 +10,27 @@ class Registers {
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registers.fill(0u)
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}
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fun setB(reg: Int, value: UByte) {
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fun setUB(reg: Int, value: UByte) {
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registers[reg] = registers[reg] and 0xff00u or value.toUShort()
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}
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fun setW(reg: Int, value: UShort) {
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fun setSB(reg: Int, value: Byte) {
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registers[reg] = registers[reg] and 0xff00u or (value.toUShort() and 0x00ffu)
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}
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fun setUW(reg: Int, value: UShort) {
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registers[reg] = value
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}
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fun getB(reg: Int) = registers[reg].toUByte()
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fun setSW(reg: Int, value: Short) {
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registers[reg] = value.toUShort()
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}
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fun getW(reg: Int) = registers[reg]
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}
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fun getUB(reg: Int) = registers[reg].toUByte()
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fun getSB(reg: Int) = registers[reg].toByte()
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fun getUW(reg: Int) = registers[reg]
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fun getSW(reg: Int) = registers[reg].toShort()
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}
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@ -17,7 +17,9 @@ SYSCALLS:
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8 = gfx_enable ; enable graphics window r0.b = 0 -> lores 320x240, r0.b = 1 -> hires 640x480
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9 = gfx_clear ; clear graphics window with shade in r0.b
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10 = gfx_plot ; plot pixel in graphics window, r0.w/r1.w contain X and Y coordinates, r2.b contains brightness
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11 = rnd ; random BYTE
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11 = rnd ; random BYTE
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12 = wait ; wait certain amount of jiffies (1/60 sec)
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13 = waitvsync ; wait on vsync
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*/
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enum class Syscall {
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@ -33,6 +35,8 @@ enum class Syscall {
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GFX_CLEAR,
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GFX_PLOT,
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RND,
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WAIT,
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WAITVSYNC
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}
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object SysCalls {
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@ -45,13 +49,13 @@ object SysCalls {
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vm.exit()
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}
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Syscall.PRINT_C -> {
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val char = vm.registers.getB(0).toInt()
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val char = vm.registers.getUB(0).toInt()
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print(Char(char))
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}
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Syscall.PRINT_S -> {
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var addr = vm.registers.getW(0).toInt()
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var addr = vm.registers.getUW(0).toInt()
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while(true) {
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val char = vm.memory.getB(addr).toInt()
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val char = vm.memory.getUB(addr).toInt()
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if(char==0)
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break
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print(Char(char))
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@ -59,29 +63,34 @@ object SysCalls {
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}
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}
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Syscall.PRINT_U8 -> {
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print(vm.registers.getB(0))
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print(vm.registers.getUB(0))
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}
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Syscall.PRINT_U16 -> {
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print(vm.registers.getW(0))
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print(vm.registers.getUW(0))
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}
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Syscall.INPUT -> {
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var input = readln()
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val maxlen = vm.registers.getB(1).toInt()
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val maxlen = vm.registers.getUB(1).toInt()
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if(maxlen>0)
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input = input.substring(0, min(input.length, maxlen))
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vm.memory.setString(vm.registers.getW(0).toInt(), input, true)
|
||||
vm.registers.setW(65535, input.length.toUShort())
|
||||
vm.memory.setString(vm.registers.getUW(0).toInt(), input, true)
|
||||
vm.registers.setUW(65535, input.length.toUShort())
|
||||
}
|
||||
Syscall.SLEEP -> {
|
||||
val duration = vm.registers.getW(0).toLong()
|
||||
val duration = vm.registers.getUW(0).toLong()
|
||||
Thread.sleep(duration)
|
||||
}
|
||||
Syscall.GFX_ENABLE -> vm.gfx_enable()
|
||||
Syscall.GFX_CLEAR -> vm.gfx_clear()
|
||||
Syscall.GFX_PLOT -> vm.gfx_plot()
|
||||
Syscall.RND -> {
|
||||
vm.registers.setB(0, (Random.nextInt() ushr 3).toUByte())
|
||||
vm.registers.setUB(0, (Random.nextInt() ushr 3).toUByte())
|
||||
}
|
||||
Syscall.WAIT -> {
|
||||
val millis = vm.registers.getUW(0).toLong() * 1000/60
|
||||
Thread.sleep(millis)
|
||||
}
|
||||
Syscall.WAITVSYNC -> vm.waitvsync()
|
||||
else -> TODO("syscall ${call.name}")
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
package prog8.vm
|
||||
|
||||
import java.awt.Toolkit
|
||||
import java.util.*
|
||||
import kotlin.math.roundToInt
|
||||
|
||||
|
|
@ -60,7 +61,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
}
|
||||
|
||||
fun exit() {
|
||||
throw ProgramExitException(registers.getW(0).toInt())
|
||||
throw ProgramExitException(registers.getUW(0).toInt())
|
||||
}
|
||||
|
||||
fun step(count: Int=1) {
|
||||
|
|
@ -132,11 +133,13 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
Opcode.AND -> InsAND(ins)
|
||||
Opcode.OR -> InsOR(ins)
|
||||
Opcode.XOR -> InsXOR(ins)
|
||||
Opcode.ASR -> InsASR(ins)
|
||||
Opcode.LSR -> InsLSR(ins)
|
||||
Opcode.LSL -> InsLSL(ins)
|
||||
Opcode.ROR -> InsROR(ins)
|
||||
Opcode.ROL -> InsROL(ins)
|
||||
Opcode.SWAP -> InsSWAP(ins)
|
||||
Opcode.CONCAT -> InsCONCAT(ins)
|
||||
Opcode.PUSH -> InsPUSH(ins)
|
||||
Opcode.POP -> InsPOP(ins)
|
||||
Opcode.COPY -> InsCOPY(ins)
|
||||
|
|
@ -148,8 +151,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
|
||||
private inline fun setResultReg(reg: Int, value: Int, type: VmDataType) {
|
||||
when(type) {
|
||||
VmDataType.BYTE -> registers.setB(reg, value.toUByte())
|
||||
VmDataType.WORD -> registers.setW(reg, value.toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(reg, value.toUByte())
|
||||
VmDataType.WORD -> registers.setUW(reg, value.toUShort())
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -158,8 +161,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
throw StackOverflowError("valuestack limit 128 exceeded")
|
||||
|
||||
val value = when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.getB(i.reg1!!).toInt()
|
||||
VmDataType.WORD -> registers.getW(i.reg1!!).toInt()
|
||||
VmDataType.BYTE -> registers.getUB(i.reg1!!).toInt()
|
||||
VmDataType.WORD -> registers.getUW(i.reg1!!).toInt()
|
||||
}
|
||||
valueStack.push(value)
|
||||
pc++
|
||||
|
|
@ -189,32 +192,32 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
|
||||
private fun InsLOADM(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, memory.getB(i.value!!))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, memory.getW(i.value!!))
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, memory.getUB(i.value!!))
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, memory.getUW(i.value!!))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsLOADI(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, memory.getB(registers.getW(i.reg2!!).toInt()))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, memory.getW(registers.getW(i.reg2!!).toInt()))
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, memory.getUB(registers.getUW(i.reg2!!).toInt()))
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, memory.getUW(registers.getUW(i.reg2!!).toInt()))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsLOADX(i: Instruction) {
|
||||
when (i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, memory.getB(i.value!! + registers.getW(i.reg2!!).toInt()))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, memory.getW(i.value!! + registers.getW(i.reg2!!).toInt()))
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, memory.getUB(i.value!! + registers.getUW(i.reg2!!).toInt()))
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, memory.getUW(i.value!! + registers.getUW(i.reg2!!).toInt()))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsLOADR(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, registers.getB(i.reg2!!))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, registers.getW(i.reg2!!))
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, registers.getUB(i.reg2!!))
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, registers.getUW(i.reg2!!))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -222,14 +225,14 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsSWAPREG(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val oldR2 = registers.getB(i.reg2!!)
|
||||
registers.setB(i.reg2, registers.getB(i.reg1!!))
|
||||
registers.setB(i.reg1, oldR2)
|
||||
val oldR2 = registers.getUB(i.reg2!!)
|
||||
registers.setUB(i.reg2, registers.getUB(i.reg1!!))
|
||||
registers.setUB(i.reg1, oldR2)
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val oldR2 = registers.getW(i.reg2!!)
|
||||
registers.setW(i.reg2, registers.getW(i.reg1!!))
|
||||
registers.setW(i.reg1, oldR2)
|
||||
val oldR2 = registers.getUW(i.reg2!!)
|
||||
registers.setUW(i.reg2, registers.getUW(i.reg1!!))
|
||||
registers.setUW(i.reg1, oldR2)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
|
|
@ -237,47 +240,47 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
|
||||
private fun InsSTOREM(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> memory.setB(i.value!!, registers.getB(i.reg1!!))
|
||||
VmDataType.WORD -> memory.setW(i.value!!, registers.getW(i.reg1!!))
|
||||
VmDataType.BYTE -> memory.setUB(i.value!!, registers.getUB(i.reg1!!))
|
||||
VmDataType.WORD -> memory.setUW(i.value!!, registers.getUW(i.reg1!!))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsSTOREI(i: Instruction) {
|
||||
when (i.type!!) {
|
||||
VmDataType.BYTE -> memory.setB(registers.getW(i.reg2!!).toInt(), registers.getB(i.reg1!!))
|
||||
VmDataType.WORD -> memory.setW(registers.getW(i.reg2!!).toInt(), registers.getW(i.reg1!!))
|
||||
VmDataType.BYTE -> memory.setUB(registers.getUW(i.reg2!!).toInt(), registers.getUB(i.reg1!!))
|
||||
VmDataType.WORD -> memory.setUW(registers.getUW(i.reg2!!).toInt(), registers.getUW(i.reg1!!))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsSTOREX(i: Instruction) {
|
||||
when (i.type!!) {
|
||||
VmDataType.BYTE -> memory.setB(registers.getW(i.reg2!!).toInt() + i.value!!, registers.getB(i.reg1!!))
|
||||
VmDataType.WORD -> memory.setW(registers.getW(i.reg2!!).toInt() + i.value!!, registers.getW(i.reg1!!))
|
||||
VmDataType.BYTE -> memory.setUB(registers.getUW(i.reg2!!).toInt() + i.value!!, registers.getUB(i.reg1!!))
|
||||
VmDataType.WORD -> memory.setUW(registers.getUW(i.reg2!!).toInt() + i.value!!, registers.getUW(i.reg1!!))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsSTOREZ(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> memory.setB(i.value!!, 0u)
|
||||
VmDataType.WORD -> memory.setW(i.value!!, 0u)
|
||||
VmDataType.BYTE -> memory.setUB(i.value!!, 0u)
|
||||
VmDataType.WORD -> memory.setUW(i.value!!, 0u)
|
||||
}
|
||||
}
|
||||
|
||||
private fun InsSTOREZI(i: Instruction) {
|
||||
when (i.type!!) {
|
||||
VmDataType.BYTE -> memory.setB(registers.getW(i.reg2!!).toInt(), 0u)
|
||||
VmDataType.WORD -> memory.setW(registers.getW(i.reg2!!).toInt(), 0u)
|
||||
VmDataType.BYTE -> memory.setUB(registers.getUW(i.reg2!!).toInt(), 0u)
|
||||
VmDataType.WORD -> memory.setUW(registers.getUW(i.reg2!!).toInt(), 0u)
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsSTOREZX(i: Instruction) {
|
||||
when (i.type!!) {
|
||||
VmDataType.BYTE -> memory.setB(registers.getW(i.reg2!!).toInt() + i.value!!, 0u)
|
||||
VmDataType.WORD -> memory.setW(registers.getW(i.reg2!!).toInt() + i.value!!, 0u)
|
||||
VmDataType.BYTE -> memory.setUB(registers.getUW(i.reg2!!).toInt() + i.value!!, 0u)
|
||||
VmDataType.WORD -> memory.setUW(registers.getUW(i.reg2!!).toInt() + i.value!!, 0u)
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -287,7 +290,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
}
|
||||
|
||||
private fun InsJUMPI(i: Instruction) {
|
||||
pc = registers.getW(i.reg1!!).toInt()
|
||||
pc = registers.getUW(i.reg1!!).toInt()
|
||||
}
|
||||
|
||||
private fun InsCALL(i: Instruction) {
|
||||
|
|
@ -297,7 +300,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
|
||||
private fun InsCALLI(i: Instruction) {
|
||||
callStack.push(pc+1)
|
||||
pc = registers.getW(i.reg1!!).toInt()
|
||||
pc = registers.getUW(i.reg1!!).toInt()
|
||||
}
|
||||
|
||||
private fun InsRETURN() {
|
||||
|
|
@ -310,13 +313,13 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsBZ(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
if(registers.getB(i.reg1!!)==0.toUByte())
|
||||
if(registers.getUB(i.reg1!!)==0.toUByte())
|
||||
pc = i.value!!
|
||||
else
|
||||
pc++
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
if(registers.getW(i.reg1!!)==0.toUShort())
|
||||
if(registers.getUW(i.reg1!!)==0.toUShort())
|
||||
pc = i.value!!
|
||||
else
|
||||
pc++
|
||||
|
|
@ -327,13 +330,13 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsBNZ(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
if(registers.getB(i.reg1!!)!=0.toUByte())
|
||||
if(registers.getUB(i.reg1!!)!=0.toUByte())
|
||||
pc = i.value!!
|
||||
else
|
||||
pc++
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
if(registers.getW(i.reg1!!)!=0.toUShort())
|
||||
if(registers.getUW(i.reg1!!)!=0.toUShort())
|
||||
pc = i.value!!
|
||||
else
|
||||
pc++
|
||||
|
|
@ -498,24 +501,24 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
|
||||
private fun InsINC(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (registers.getB(i.reg1)+1u).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (registers.getW(i.reg1)+1u).toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (registers.getUB(i.reg1)+1u).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (registers.getUW(i.reg1)+1u).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsDEC(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (registers.getB(i.reg1)-1u).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (registers.getW(i.reg1)-1u).toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (registers.getUB(i.reg1)-1u).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (registers.getUW(i.reg1)-1u).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsNEG(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (-registers.getB(i.reg1).toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (-registers.getW(i.reg1).toInt()).toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (-registers.getUB(i.reg1).toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (-registers.getUW(i.reg1).toInt()).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -553,8 +556,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
}
|
||||
|
||||
private fun arithByte(operator: String, reg1: Int, reg2: Int, reg3: Int?, value: UByte?) {
|
||||
val left = registers.getB(reg2)
|
||||
val right = value ?: registers.getB(reg3!!)
|
||||
val left = registers.getUB(reg2)
|
||||
val right = value ?: registers.getUB(reg3!!)
|
||||
val result = when(operator) {
|
||||
"+" -> left + right
|
||||
"-" -> left - right
|
||||
|
|
@ -569,12 +572,12 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
}
|
||||
else -> TODO("operator $operator")
|
||||
}
|
||||
registers.setB(reg1, result.toUByte())
|
||||
registers.setUB(reg1, result.toUByte())
|
||||
}
|
||||
|
||||
private fun arithWord(operator: String, reg1: Int, reg2: Int, reg3: Int?, value: UShort?) {
|
||||
val left = registers.getW(reg2)
|
||||
val right = value ?: registers.getW(reg3!!)
|
||||
val left = registers.getUW(reg2)
|
||||
val right = value ?: registers.getUW(reg3!!)
|
||||
val result = when(operator) {
|
||||
"+" -> left + right
|
||||
"-" -> left - right
|
||||
|
|
@ -589,7 +592,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
}
|
||||
else -> TODO("operator $operator")
|
||||
}
|
||||
registers.setW(reg1, result.toUShort())
|
||||
registers.setUW(reg1, result.toUShort())
|
||||
}
|
||||
|
||||
private fun InsSUB(i: Instruction) {
|
||||
|
|
@ -602,7 +605,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
|
||||
private fun InsEXT(i: Instruction) {
|
||||
when(i.type!!){
|
||||
VmDataType.BYTE -> registers.setW(i.reg1!!, registers.getB(i.reg1).toUShort())
|
||||
VmDataType.BYTE -> registers.setUW(i.reg1!!, registers.getUB(i.reg1).toUShort())
|
||||
VmDataType.WORD -> TODO("ext.w requires 32 bits registers")
|
||||
}
|
||||
pc++
|
||||
|
|
@ -610,7 +613,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
|
||||
private fun InsEXTS(i: Instruction) {
|
||||
when(i.type!!){
|
||||
VmDataType.BYTE -> registers.setW(i.reg1!!, (registers.getB(i.reg1).toByte()).toUShort())
|
||||
VmDataType.BYTE -> registers.setSW(i.reg1!!, registers.getSB(i.reg1).toShort())
|
||||
VmDataType.WORD -> TODO("ext.w requires 32 bits registers")
|
||||
}
|
||||
pc++
|
||||
|
|
@ -619,8 +622,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsAND(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left and right).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left and right).toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left and right).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left and right).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -628,8 +631,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsOR(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left or right).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left or right).toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left or right).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left or right).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -637,8 +640,17 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsXOR(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left xor right).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left xor right).toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left xor right).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left xor right).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsASR(i: Instruction) {
|
||||
val (left: Int, right: Int) = getLogicalOperandsS(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setSB(i.reg1!!, (left shr right).toByte())
|
||||
VmDataType.WORD -> registers.setSW(i.reg1!!, (left shr right).toShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -646,8 +658,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsLSR(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left shr right.toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left shr right.toInt()).toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left shr right.toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left shr right.toInt()).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -655,8 +667,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsLSL(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left shl right.toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left shl right.toInt()).toUShort())
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left shl right.toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left shl right.toInt()).toUShort())
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -664,8 +676,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsROR(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left.rotateRight(right.toInt()).toUByte()))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left.rotateRight(right.toInt()).toUShort()))
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left.rotateRight(right.toInt()).toUByte()))
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left.rotateRight(right.toInt()).toUShort()))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -673,8 +685,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsROL(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setB(i.reg1!!, (left.rotateLeft(right.toInt()).toUByte()))
|
||||
VmDataType.WORD -> registers.setW(i.reg1!!, (left.rotateLeft(right.toInt()).toUShort()))
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left.rotateLeft(right.toInt()).toUByte()))
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left.rotateLeft(right.toInt()).toUShort()))
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
|
@ -682,9 +694,21 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsSWAP(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val value = registers.getW(i.reg2!!)
|
||||
val value = registers.getUW(i.reg2!!)
|
||||
val newValue = value.toUByte()*256u + (value.toInt() ushr 8).toUInt()
|
||||
registers.setW(i.reg1!!, newValue.toUShort())
|
||||
registers.setUW(i.reg1!!, newValue.toUShort())
|
||||
}
|
||||
VmDataType.WORD -> TODO("swap.w requires 32-bits registers")
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsCONCAT(i: Instruction) {
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val msb = registers.getUB(i.reg2!!)
|
||||
val lsb = registers.getUB(i.reg3!!)
|
||||
registers.setUW(i.reg1!!, ((msb.toInt() shl 8) or lsb.toInt()).toUShort())
|
||||
}
|
||||
VmDataType.WORD -> TODO("swap.w requires 32-bits registers")
|
||||
}
|
||||
|
|
@ -696,13 +720,13 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private fun InsCOPYZ(i: Instruction) = doCopy(i.reg1!!, i.reg2!!, null, true)
|
||||
|
||||
private fun doCopy(reg1: Int, reg2: Int, length: Int?, untilzero: Boolean) {
|
||||
var from = registers.getW(reg1).toInt()
|
||||
var to = registers.getW(reg2).toInt()
|
||||
var from = registers.getUW(reg1).toInt()
|
||||
var to = registers.getUW(reg2).toInt()
|
||||
if(untilzero) {
|
||||
while(true) {
|
||||
val char = memory.getB(from).toInt()
|
||||
memory.setB(to, char.toUByte())
|
||||
if(char==0)
|
||||
val char = memory.getUB(from)
|
||||
memory.setUB(to, char)
|
||||
if(char.toInt()==0)
|
||||
break
|
||||
from++
|
||||
to++
|
||||
|
|
@ -710,8 +734,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
} else {
|
||||
var len = length!!
|
||||
while(len>0) {
|
||||
val char = memory.getB(from).toInt()
|
||||
memory.setB(to, char.toUByte())
|
||||
val char = memory.getUB(from)
|
||||
memory.setUB(to, char)
|
||||
from++
|
||||
to++
|
||||
len--
|
||||
|
|
@ -722,40 +746,49 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
|
||||
private fun getBranchOperands(i: Instruction): Pair<Int, Int> {
|
||||
return when(i.type) {
|
||||
VmDataType.BYTE -> Pair(registers.getB(i.reg1!!).toInt(), registers.getB(i.reg2!!).toInt())
|
||||
VmDataType.WORD -> Pair(registers.getW(i.reg1!!).toInt(), registers.getW(i.reg2!!).toInt())
|
||||
VmDataType.BYTE -> Pair(registers.getSB(i.reg1!!).toInt(), registers.getSB(i.reg2!!).toInt())
|
||||
VmDataType.WORD -> Pair(registers.getSW(i.reg1!!).toInt(), registers.getSW(i.reg2!!).toInt())
|
||||
null -> throw IllegalArgumentException("need type for branch instruction")
|
||||
}
|
||||
}
|
||||
|
||||
private fun getBranchOperandsU(i: Instruction): Pair<UInt, UInt> {
|
||||
return when(i.type) {
|
||||
VmDataType.BYTE -> Pair(registers.getB(i.reg1!!).toUInt(), registers.getB(i.reg2!!).toUInt())
|
||||
VmDataType.WORD -> Pair(registers.getW(i.reg1!!).toUInt(), registers.getW(i.reg2!!).toUInt())
|
||||
VmDataType.BYTE -> Pair(registers.getUB(i.reg1!!).toUInt(), registers.getUB(i.reg2!!).toUInt())
|
||||
VmDataType.WORD -> Pair(registers.getUW(i.reg1!!).toUInt(), registers.getUW(i.reg2!!).toUInt())
|
||||
null -> throw IllegalArgumentException("need type for branch instruction")
|
||||
}
|
||||
}
|
||||
|
||||
private fun getLogicalOperandsU(i: Instruction): Pair<UInt, UInt> {
|
||||
return when(i.type) {
|
||||
VmDataType.BYTE -> Pair(registers.getB(i.reg2!!).toUInt(), registers.getB(i.reg3!!).toUInt())
|
||||
VmDataType.WORD -> Pair(registers.getW(i.reg2!!).toUInt(), registers.getW(i.reg3!!).toUInt())
|
||||
VmDataType.BYTE -> Pair(registers.getUB(i.reg2!!).toUInt(), registers.getUB(i.reg3!!).toUInt())
|
||||
VmDataType.WORD -> Pair(registers.getUW(i.reg2!!).toUInt(), registers.getUW(i.reg3!!).toUInt())
|
||||
null -> throw IllegalArgumentException("need type for logical instruction")
|
||||
}
|
||||
}
|
||||
|
||||
private fun getLogicalOperandsS(i: Instruction): Pair<Int, Int> {
|
||||
return when(i.type) {
|
||||
VmDataType.BYTE -> Pair(registers.getSB(i.reg2!!).toInt(), registers.getSB(i.reg3!!).toInt())
|
||||
VmDataType.WORD -> Pair(registers.getSW(i.reg2!!).toInt(), registers.getSW(i.reg3!!).toInt())
|
||||
null -> throw IllegalArgumentException("need type for logical instruction")
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
private fun getSetOnConditionOperands(ins: Instruction): Triple<Int, Int, Int> {
|
||||
return when(ins.type) {
|
||||
VmDataType.BYTE -> Triple(ins.reg1!!, registers.getB(ins.reg2!!).toInt(), registers.getB(ins.reg3!!).toInt())
|
||||
VmDataType.WORD -> Triple(ins.reg1!!, registers.getW(ins.reg2!!).toInt(), registers.getW(ins.reg3!!).toInt())
|
||||
VmDataType.BYTE -> Triple(ins.reg1!!, registers.getSB(ins.reg2!!).toInt(), registers.getSB(ins.reg3!!).toInt())
|
||||
VmDataType.WORD -> Triple(ins.reg1!!, registers.getSW(ins.reg2!!).toInt(), registers.getSW(ins.reg3!!).toInt())
|
||||
null -> throw IllegalArgumentException("need type for branch instruction")
|
||||
}
|
||||
}
|
||||
|
||||
private fun getSetOnConditionOperandsU(ins: Instruction): Triple<Int, UInt, UInt> {
|
||||
return when(ins.type) {
|
||||
VmDataType.BYTE -> Triple(ins.reg1!!, registers.getB(ins.reg2!!).toUInt(), registers.getB(ins.reg3!!).toUInt())
|
||||
VmDataType.WORD -> Triple(ins.reg1!!, registers.getW(ins.reg2!!).toUInt(), registers.getW(ins.reg3!!).toUInt())
|
||||
VmDataType.BYTE -> Triple(ins.reg1!!, registers.getUB(ins.reg2!!).toUInt(), registers.getUB(ins.reg3!!).toUInt())
|
||||
VmDataType.WORD -> Triple(ins.reg1!!, registers.getUW(ins.reg2!!).toUInt(), registers.getUW(ins.reg3!!).toUInt())
|
||||
null -> throw IllegalArgumentException("need type for branch instruction")
|
||||
}
|
||||
}
|
||||
|
|
@ -763,7 +796,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
private var window: GraphicsWindow? = null
|
||||
|
||||
fun gfx_enable() {
|
||||
window = when(registers.getB(0).toInt()) {
|
||||
window = when(registers.getUB(0).toInt()) {
|
||||
0 -> GraphicsWindow(320, 240, 3)
|
||||
1 -> GraphicsWindow(640, 480, 2)
|
||||
else -> throw IllegalArgumentException("invalid screen mode")
|
||||
|
|
@ -772,14 +805,18 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
|||
}
|
||||
|
||||
fun gfx_clear() {
|
||||
window?.clear(registers.getB(0).toInt())
|
||||
window?.clear(registers.getUB(0).toInt())
|
||||
}
|
||||
|
||||
fun gfx_plot() {
|
||||
window?.plot(registers.getW(0).toInt(), registers.getW(1).toInt(), registers.getB(2).toInt())
|
||||
window?.plot(registers.getUW(0).toInt(), registers.getUW(1).toInt(), registers.getUB(2).toInt())
|
||||
}
|
||||
|
||||
fun gfx_close() {
|
||||
window?.close()
|
||||
}
|
||||
|
||||
fun waitvsync() {
|
||||
Toolkit.getDefaultToolkit().sync() // not really the same as wait on vsync, but there's noting else
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user