use inc/ina instead of adc

This commit is contained in:
Irmen de Jong 2021-11-29 00:07:15 +01:00
parent cafab98d10
commit 45b8762188
4 changed files with 11 additions and 10 deletions

View File

@ -1998,7 +1998,13 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
}
TargetStorageKind.REGISTER -> {
when(target.register!!) {
RegisterOrPair.A -> asmgen.out(" eor #255 | clc | adc #1")
RegisterOrPair.A -> {
if(asmgen.isTargetCpu(CpuType.CPU65c02))
asmgen.out(" eor #255 | ina")
else
asmgen.out(" eor #255 | clc | adc #1")
}
RegisterOrPair.X -> asmgen.out(" txa | eor #255 | tax | inx")
RegisterOrPair.Y -> asmgen.out(" tya | eor #255 | tay | iny")
else -> throw AssemblyError("invalid reg dt for byte negate")

View File

@ -110,7 +110,6 @@ internal class ConstantIdentifierReplacer(private val program: Program, private
override fun before(decl: VarDecl, parent: Node): Iterable<IAstModification> {
// the initializer value can't refer to the variable itself (recursive definition)
// TODO: use call graph for this?
if(decl.value?.referencesIdentifier(listOf(decl.name)) == true || decl.arraysize?.indexExpr?.referencesIdentifier(listOf(decl.name)) == true) {
errors.err("recursive var declaration", decl.position)
return noModifications

View File

@ -808,11 +808,8 @@ _done
sta cx16.VERA_ADDR_L
bcc +
inc cx16.VERA_ADDR_M
+ lda x
clc
adc #1
sta x
bcc +
+ inc x
bne +
inc x+1
+ dey
bne -

View File

@ -565,9 +565,8 @@ asmsub print_w (word value @ AY) clobbers(A,Y) {
tay
pla
eor #255
clc
adc #1
bcc +
ina
bne +
iny
+ bra print_uw
}}