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added more missing codegen for bit shifts
This commit is contained in:
Irmen de Jong
parent
64254e758d
commit
47485e4b49
@ -512,86 +512,135 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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private fun optimizedBitshiftExpr(expr: PtBinaryExpression, target: AsmAssignTarget): Boolean {
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val signed = expr.left.type in SignedDatatypes
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val shifts = expr.right.asConstInteger()
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if(shifts!=null) {
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val dt = expr.left.type
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val dt = expr.left.type
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if(shifts==null) {
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// bit shifts with variable shifts
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when(expr.right.type) {
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in ByteDatatypes -> {
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assignExpressionToRegister(expr.right, RegisterOrPair.A, false)
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}
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in WordDatatypes -> {
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assignExpressionToRegister(expr.right, RegisterOrPair.AY, false)
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asmgen.out("""
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cpy #0
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beq +
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lda #127
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+""")
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}
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else -> throw AssemblyError("weird shift value type")
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}
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asmgen.out(" pha")
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if(dt in ByteDatatypes) {
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val signed = dt == DataType.BYTE
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assignExpressionToRegister(expr.left, RegisterOrPair.A, signed)
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if(shifts in 0..7) {
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require(dt==DataType.UBYTE)
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if (expr.operator == "<<") {
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repeat(shifts) {
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asmgen.out(" asl a")
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}
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} else {
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if (signed && shifts > 0) {
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asmgen.out(" ldy #$shifts | jsr math.lsr_byte_A")
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} else {
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asmgen.out(" ply")
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if(expr.operator==">>")
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if(signed)
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asmgen.out(" jsr math.lsr_byte_A")
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else
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asmgen.out(" jsr math.lsr_ubyte_A")
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else
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asmgen.out(" jsr math.asl_byte_A")
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assignRegisterByte(target, CpuRegister.A, signed)
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return true
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} else {
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assignExpressionToRegister(expr.left, RegisterOrPair.AY, signed)
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asmgen.out(" plx")
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if(expr.operator==">>")
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if(signed)
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asmgen.out(" jsr math.lsr_word_AY")
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else
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asmgen.out(" jsr math.lsr_uword_AY")
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else
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asmgen.out(" jsr math.asl_word_AY")
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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}
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else {
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// bit shift with constant value
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if(dt in ByteDatatypes) {
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assignExpressionToRegister(expr.left, RegisterOrPair.A, signed)
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when (shifts) {
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in 0..7 -> {
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require(dt==DataType.UBYTE)
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if (expr.operator == "<<") {
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repeat(shifts) {
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asmgen.out(" lsr a")
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asmgen.out(" asl a")
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}
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} else {
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if (signed && shifts > 0) {
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asmgen.out(" ldy #$shifts | jsr math.lsr_byte_A")
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} else {
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repeat(shifts) {
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asmgen.out(" lsr a")
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}
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}
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}
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assignRegisterByte(target, CpuRegister.A, signed)
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return true
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}
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assignRegisterByte(target, CpuRegister.A, signed)
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return true
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} else {
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if(signed && expr.operator==">>") {
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TODO("signed byte >> overshift should have been compiled away?")
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} else {
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asmgen.out(" lda #0")
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else -> {
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if(signed && expr.operator==">>") {
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TODO("signed byte >> overshift should have been compiled away?")
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} else {
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asmgen.out(" lda #0")
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}
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assignRegisterByte(target, CpuRegister.A, signed)
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return true
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}
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assignRegisterByte(target, CpuRegister.A, signed)
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return true
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}
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} else if(dt in WordDatatypes) {
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val signed = dt == DataType.WORD
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assignExpressionToRegister(expr.left, RegisterOrPair.AY, signed)
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if(shifts in 0..7) {
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if(expr.operator=="<<") {
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if(shifts>0) {
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asmgen.out(" sty P8ZP_SCRATCH_B1")
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repeat(shifts) {
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asmgen.out(" asl a | rol P8ZP_SCRATCH_B1")
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}
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asmgen.out(" ldy P8ZP_SCRATCH_B1")
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}
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} else {
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if(signed && shifts>0) {
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asmgen.out(" ldx #$shifts | jsr math.lsr_word_AY")
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} else {
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when (shifts) {
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in 0..7 -> {
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if(expr.operator=="<<") {
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if(shifts>0) {
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asmgen.out(" sty P8ZP_SCRATCH_B1")
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repeat(shifts) {
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asmgen.out(" lsr P8ZP_SCRATCH_B1 | ror a")
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asmgen.out(" asl a | rol P8ZP_SCRATCH_B1")
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}
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asmgen.out(" ldy P8ZP_SCRATCH_B1")
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}
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} else {
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if(signed && shifts>0) {
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asmgen.out(" ldx #$shifts | jsr math.lsr_word_AY")
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} else {
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if(shifts>0) {
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asmgen.out(" sty P8ZP_SCRATCH_B1")
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repeat(shifts) {
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asmgen.out(" lsr P8ZP_SCRATCH_B1 | ror a")
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}
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asmgen.out(" ldy P8ZP_SCRATCH_B1")
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}
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}
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}
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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} else if (shifts in 8..15) {
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if(expr.operator == "<<") {
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// msb = lsb << (shifts-8), lsb = 0
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repeat(shifts-8) {
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asmgen.out(" asl a")
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in 8..15 -> {
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if(expr.operator == "<<") {
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// msb = lsb << (shifts-8), lsb = 0
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repeat(shifts-8) {
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asmgen.out(" asl a")
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}
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asmgen.out(" tay | lda #0")
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} else {
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asmgen.out(" ldx #$shifts | jsr math.lsr_word_AY")
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}
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asmgen.out(" tay | lda #0")
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} else {
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asmgen.out(" ldx #$shifts | jsr math.lsr_word_AY")
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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else {
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if(signed && expr.operator==">>") {
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TODO("signed word >> overshift should have been compiled away?")
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} else {
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asmgen.out(" lda #0 | ldy #0")
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else -> {
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if(signed && expr.operator==">>") {
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TODO("signed word >> overshift should have been compiled away?")
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} else {
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asmgen.out(" lda #0 | ldy #0")
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}
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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assignRegisterpairWord(target, RegisterOrPair.AY)
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return true
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}
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}
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}
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@ -751,37 +751,64 @@ mul_word_640 .proc
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lsr_byte_A .proc
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; -- lsr signed byte in A times the value in Y (>1)
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cmp #0
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bmi _negative
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- lsr a
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dey
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bne -
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rts
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_negative sec
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bpl lsr_ubyte_A
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- sec
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ror a
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dey
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bne _negative
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bne -
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rts
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.pend
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lsr_ubyte_A .proc
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; -- lsr unsigned byte in A times the value in Y (>1)
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- lsr a
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dey
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bne -
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rts
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.pend
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asl_byte_A .proc
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; -- asl any byte in A times the value in Y (>1)
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- asl a
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dey
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bne -
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rts
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.pend
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lsr_word_AY .proc
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; -- lsr signed word in AY times the value in X (>1)
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sta P8ZP_SCRATCH_B1
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tya
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bmi _negative
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- lsr a
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ror P8ZP_SCRATCH_B1
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dex
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bne -
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tay
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lda P8ZP_SCRATCH_B1
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rts
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cpy #0
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bpl lsr_uword_AY
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sty P8ZP_SCRATCH_B1
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_negative sec
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ror a
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ror P8ZP_SCRATCH_B1
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ror a
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dex
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bne _negative
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tay
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lda P8ZP_SCRATCH_B1
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ldy P8ZP_SCRATCH_B1
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rts
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.pend
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lsr_uword_AY .proc
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; -- lsr unsigned word in AY times the value in X (>1)
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sty P8ZP_SCRATCH_B1
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- lsr P8ZP_SCRATCH_B1
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ror a
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dex
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bne -
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ldy P8ZP_SCRATCH_B1
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rts
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.pend
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asl_word_AY .proc
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; -- asl any word in AY times the value in X (>1)
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sty P8ZP_SCRATCH_B1
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- asl a
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rol P8ZP_SCRATCH_B1
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dex
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bne -
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ldy P8ZP_SCRATCH_B1
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rts
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.pend
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@ -1,6 +1,9 @@
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TODO
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====
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- (branch): fix float expressions codegen, it relied heavily on the evalstack
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- (branch): improve integer expression codegen even more to support even more cases?
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- IR: instructions that do type conversion (SZ etc, CONCAT, SGN) should put the result in a DIFFERENT register.
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- IR: reduce the number of branch instructions (gradually), replace with CMP(I) + status branch instruction
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@ -5,15 +5,32 @@ main
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{
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sub start()
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{
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byte zc = -55
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uword zc = 54321
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ubyte zb = 123
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ubyte shift = 2
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when zc*3 {
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123 -> zc++
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124 -> zc++
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125 -> zc++
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121 -> zc++
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120 -> zc++
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else -> zc++
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}
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txt.print_uw(zc<<shift)
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txt.nl()
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txt.print_uw(zc>>shift)
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txt.nl()
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txt.print_ub(zb<<shift)
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txt.nl()
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txt.print_ub(zb>>shift)
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txt.nl()
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word szc = -12345
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byte szb = -123
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txt.print_w(szc<<shift)
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txt.nl()
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txt.print_w(szc>>shift)
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txt.nl()
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txt.print_b(szb<<shift)
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txt.nl()
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txt.print_b(szb>>shift)
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txt.nl()
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; cx16.r1L = (zc<<shift) as ubyte
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; txt.print_ub(cx16.r1L)
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}
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}
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