mirror of
https://github.com/irmen/prog8.git
synced 2024-11-28 10:51:14 +00:00
fix IR if expression sometimes lacking a cmpi after calculation of the condition value
VM/IR: add a returni immediate value return instruction to replace certain returnr's
This commit is contained in:
parent
09cbdf410a
commit
4a47e15b1c
@ -1395,12 +1395,14 @@ class IRCodeGen(
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private fun ifWithElse_IntegerCond(ifElse: PtIfElse): List<IRCodeChunkBase> {
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private fun ifWithElse_IntegerCond(ifElse: PtIfElse): List<IRCodeChunkBase> {
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val result = mutableListOf<IRCodeChunkBase>()
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val result = mutableListOf<IRCodeChunkBase>()
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fun translateSimple(condition: PtExpression, jumpFalseOpcode: Opcode) {
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fun translateSimple(condition: PtExpression, jumpFalseOpcode: Opcode, addCmpiZero: Boolean) {
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if(condition is PtBuiltinFunctionCall && condition.name.startsWith("prog8_ifelse_bittest_"))
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if(condition is PtBuiltinFunctionCall && condition.name.startsWith("prog8_ifelse_bittest_"))
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throw AssemblyError("IR codegen doesn't have special instructions for dedicated BIT tests and should just still use normal AND")
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throw AssemblyError("IR codegen doesn't have special instructions for dedicated BIT tests and should just still use normal AND")
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val tr = expressionEval.translateExpression(condition)
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val tr = expressionEval.translateExpression(condition)
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if(addCmpiZero)
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tr.chunks.last().instructions.add(IRInstruction(Opcode.CMPI, tr.dt, reg1 = tr.resultReg, immediate = 0))
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result += tr.chunks
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result += tr.chunks
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if(ifElse.hasElse()) {
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if(ifElse.hasElse()) {
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val elseLabel = createLabelName()
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val elseLabel = createLabelName()
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@ -1420,7 +1422,7 @@ class IRCodeGen(
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fun translateBinExpr(condition: PtBinaryExpression) {
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fun translateBinExpr(condition: PtBinaryExpression) {
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if(condition.operator in LogicalOperators)
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if(condition.operator in LogicalOperators)
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return translateSimple(condition, Opcode.BSTEQ)
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return translateSimple(condition, Opcode.BSTEQ, false)
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val signed = condition.left.type in SignedDatatypes
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val signed = condition.left.type in SignedDatatypes
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val elseBranchFirstReg: Int
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val elseBranchFirstReg: Int
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@ -1559,18 +1561,21 @@ class IRCodeGen(
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when(val cond=ifElse.condition) {
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when(val cond=ifElse.condition) {
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is PtBool -> {
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is PtBool -> {
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// normally this will be optimized away, but not with -noopt
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// normally this will be optimized away, but not with -noopt
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translateSimple(cond, Opcode.BSTEQ)
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translateSimple(cond, Opcode.BSTEQ, false)
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}
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}
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is PtTypeCast -> {
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is PtTypeCast -> {
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require(cond.type==DataType.BOOL && cond.value.type in NumericDatatypes)
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require(cond.type==DataType.BOOL && cond.value.type in NumericDatatypes)
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translateSimple(cond, Opcode.BSTEQ)
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translateSimple(cond, Opcode.BSTEQ, false)
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}
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}
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is PtIdentifier, is PtArrayIndexer, is PtBuiltinFunctionCall, is PtFunctionCall, is PtContainmentCheck -> {
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is PtIdentifier, is PtArrayIndexer, is PtContainmentCheck -> {
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translateSimple(cond, Opcode.BSTEQ)
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translateSimple(cond, Opcode.BSTEQ, false)
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}
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is PtBuiltinFunctionCall, is PtFunctionCall -> {
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translateSimple(cond, Opcode.BSTEQ, true)
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}
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}
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is PtPrefix -> {
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is PtPrefix -> {
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require(cond.operator=="not")
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require(cond.operator=="not")
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translateSimple(cond.value, Opcode.BSTNE)
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translateSimple(cond.value, Opcode.BSTNE, false)
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}
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}
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is PtBinaryExpression -> {
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is PtBinaryExpression -> {
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translateBinExpr(cond)
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translateBinExpr(cond)
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@ -1648,14 +1653,22 @@ class IRCodeGen(
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addInstr(result, IRInstruction(Opcode.RETURN), null)
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addInstr(result, IRInstruction(Opcode.RETURN), null)
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} else {
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} else {
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if(value.type==DataType.FLOAT) {
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if(value.type==DataType.FLOAT) {
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val tr = expressionEval.translateExpression(value)
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if(value is PtNumber) {
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addToResult(result, tr, -1, tr.resultFpReg)
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addInstr(result, IRInstruction(Opcode.RETURNI, IRDataType.FLOAT, immediateFp = value.number), null)
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addInstr(result, IRInstruction(Opcode.RETURNR, IRDataType.FLOAT, fpReg1 = tr.resultFpReg), null)
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} else {
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val tr = expressionEval.translateExpression(value)
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addToResult(result, tr, -1, tr.resultFpReg)
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addInstr(result, IRInstruction(Opcode.RETURNR, IRDataType.FLOAT, fpReg1 = tr.resultFpReg), null)
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}
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}
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}
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else {
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else {
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val tr = expressionEval.translateExpression(value)
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if(value.asConstInteger()!=null) {
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addToResult(result, tr, tr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.RETURNI, irType(value.type), immediate = value.asConstInteger()), null)
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addInstr(result, IRInstruction(Opcode.RETURNR, irType(value.type) , reg1=tr.resultReg), null)
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} else {
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val tr = expressionEval.translateExpression(value)
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addToResult(result, tr, tr.resultReg, -1)
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addInstr(result, IRInstruction(Opcode.RETURNR, irType(value.type), reg1 = tr.resultReg), null)
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}
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}
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}
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}
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}
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return result
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return result
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@ -299,7 +299,7 @@ class IRPeepholeOptimizer(private val irprog: IRProgram) {
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}
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}
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// remove useless RETURN
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// remove useless RETURN
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if(idx>0 && (ins.opcode == Opcode.RETURN || ins.opcode==Opcode.RETURNR)) {
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if(idx>0 && (ins.opcode == Opcode.RETURN || ins.opcode==Opcode.RETURNR || ins.opcode==Opcode.RETURNI)) {
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val previous = chunk.instructions[idx-1]
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val previous = chunk.instructions[idx-1]
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if(previous.opcode in OpcodesThatJump) {
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if(previous.opcode in OpcodesThatJump) {
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chunk.instructions.removeAt(idx)
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chunk.instructions.removeAt(idx)
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@ -1,9 +1,8 @@
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TODO
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TODO
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====
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====
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VM/IR: fix return value passing from %ir routines? (diskio.exists routine always returns true)
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replace zsound example by a zsmkit example
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contribute a short how-to to the zsmkit repo for building a suitable blob
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make better zsmkit example
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write a howto for integrating third party library code like zsmkit and vtui
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write a howto for integrating third party library code like zsmkit and vtui
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Improve register load order in subroutine call args assignments:
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Improve register load order in subroutine call args assignments:
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@ -1,30 +1,60 @@
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%import diskio
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%import textio
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%import textio
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;%import gfx_hires4
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%import diskio
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%option no_sysinit
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%option no_sysinit
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%zeropage basicsafe
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%zeropage basicsafe
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main {
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main {
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sub start() {
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sub start() {
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txt.print_bool(diskio.exists("doesntexist.prg"))
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txt.print_ub(exists_byte("test.prg"))
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txt.spc()
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txt.print_ub(exists_byte("doesntexist.xxx"))
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txt.nl()
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txt.nl()
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txt.print_bool(diskio.exists("test.prg"))
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txt.print_bool(exists_bool("test.prg"))
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txt.spc()
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txt.print_bool(exists_bool("doesntexist.xxx"))
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txt.nl()
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txt.nl()
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txt.print_bool(exists1("test.prg"))
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txt.spc()
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txt.print_bool(exists1("doesntexist.xxx"))
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txt.nl()
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txt.print_bool(exists2("test.prg"))
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txt.spc()
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txt.print_bool(exists2("doesntexist.xxx"))
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txt.nl()
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}
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diskio.f_open_w("dump.bin")
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sub exists1(str filename) -> bool {
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diskio.f_close_w()
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; -- returns true if the given file exists on the disk, otherwise false
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diskio.f_close_w()
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if exists_byte(filename)!=0 {
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diskio.f_close_w()
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return true
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diskio.f_close_w()
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}
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return false
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}
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; gfx_hires4.graphics_mode()
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sub exists2(str filename) -> bool {
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; gfx_hires4.circle(300, 250, 200, 3)
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; -- returns true if the given file exists on the disk, otherwise false
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; gfx_hires4.rect(320, 10, 20, 200, 3)
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if exists_bool(filename) {
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; gfx_hires4.fill(310, 310, 2)
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return true
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;
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}
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; repeat {
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return false
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; }
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}
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sub exists_bool(str name) -> bool {
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%ir {{
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loadm.w r65535,main.exists_bool.name
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syscall 52 (r65535.w): r0.b
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returnr.b r0
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}}
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}
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sub exists_byte(str name) -> ubyte {
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%ir {{
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loadm.w r65535,main.exists_byte.name
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syscall 52 (r65535.w): r0.b
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returnr.b r0
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}}
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}
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}
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}
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}
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@ -82,6 +82,7 @@ syscall number (argument register list) [: resultreg.type]
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Always preceded by parameter setup and preparecall instructions
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Always preceded by parameter setup and preparecall instructions
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return - restore last saved instruction location and continue at that instruction. No return value.
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return - restore last saved instruction location and continue at that instruction. No return value.
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returnr reg1 - like return, but also returns the value in reg1 to the caller
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returnr reg1 - like return, but also returns the value in reg1 to the caller
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returni number - like return, but also returns the immediate value to the caller
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@ -289,6 +290,7 @@ enum class Opcode {
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SYSCALL,
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SYSCALL,
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RETURN,
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RETURN,
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RETURNR,
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RETURNR,
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RETURNI,
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BSTCC,
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BSTCC,
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BSTCS,
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BSTCS,
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@ -428,7 +430,8 @@ val OpcodesThatJump = arrayOf(
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Opcode.JUMP,
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Opcode.JUMP,
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Opcode.JUMPI,
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Opcode.JUMPI,
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Opcode.RETURN,
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Opcode.RETURN,
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Opcode.RETURNR
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Opcode.RETURNR,
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Opcode.RETURNI
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)
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)
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val OpcodesThatBranch = arrayOf(
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val OpcodesThatBranch = arrayOf(
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@ -436,6 +439,7 @@ val OpcodesThatBranch = arrayOf(
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Opcode.JUMPI,
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Opcode.JUMPI,
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Opcode.RETURN,
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Opcode.RETURN,
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Opcode.RETURNR,
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Opcode.RETURNR,
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Opcode.RETURNI,
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Opcode.CALLI,
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Opcode.CALLI,
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Opcode.CALL,
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Opcode.CALL,
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Opcode.SYSCALL,
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Opcode.SYSCALL,
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@ -647,7 +651,8 @@ val instructionFormats = mutableMapOf(
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Opcode.CALL to InstructionFormat.from("N,call"),
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Opcode.CALL to InstructionFormat.from("N,call"),
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Opcode.SYSCALL to InstructionFormat.from("N,syscall"),
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Opcode.SYSCALL to InstructionFormat.from("N,syscall"),
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Opcode.RETURN to InstructionFormat.from("N"),
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Opcode.RETURN to InstructionFormat.from("N"),
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Opcode.RETURNR to InstructionFormat.from("BW,>r1 | F,>fr1"),
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Opcode.RETURNR to InstructionFormat.from("BW,<r1 | F,<fr1"),
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Opcode.RETURNI to InstructionFormat.from("BW,<i | F,<i"),
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Opcode.BSTCC to InstructionFormat.from("N,<a"),
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Opcode.BSTCC to InstructionFormat.from("N,<a"),
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Opcode.BSTCS to InstructionFormat.from("N,<a"),
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Opcode.BSTCS to InstructionFormat.from("N,<a"),
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Opcode.BSTEQ to InstructionFormat.from("N,<a"),
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Opcode.BSTEQ to InstructionFormat.from("N,<a"),
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@ -145,7 +145,7 @@ class IRProgram(val name: String,
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// link all jump and branching instructions to their target
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// link all jump and branching instructions to their target
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chunk.instructions.forEach {
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chunk.instructions.forEach {
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if(it.opcode in OpcodesThatBranch && it.opcode!=Opcode.JUMPI && it.opcode!=Opcode.RETURN && it.opcode!=Opcode.RETURNR && it.labelSymbol!=null) {
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if(it.opcode in OpcodesThatBranch && it.opcode!=Opcode.JUMPI && it.opcode!=Opcode.RETURN && it.opcode!=Opcode.RETURNR && it.opcode!=Opcode.RETURNI && it.labelSymbol!=null) {
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if(it.labelSymbol.startsWith('$') || it.labelSymbol.first().isDigit()) {
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if(it.labelSymbol.startsWith('$') || it.labelSymbol.first().isDigit()) {
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// it's a call to an address (romsub most likely)
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// it's a call to an address (romsub most likely)
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requireNotNull(it.address)
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requireNotNull(it.address)
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@ -213,6 +213,7 @@ class VirtualMachine(irProgram: IRProgram) {
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Opcode.SYSCALL -> InsSYSCALL(ins)
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Opcode.SYSCALL -> InsSYSCALL(ins)
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Opcode.RETURN -> InsRETURN()
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Opcode.RETURN -> InsRETURN()
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Opcode.RETURNR -> InsRETURNR(ins)
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Opcode.RETURNR -> InsRETURNR(ins)
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Opcode.RETURNI -> InsRETURNI(ins)
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Opcode.BSTCC -> InsBSTCC(ins)
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Opcode.BSTCC -> InsBSTCC(ins)
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Opcode.BSTCS -> InsBSTCS(ins)
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Opcode.BSTCS -> InsBSTCS(ins)
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Opcode.BSTEQ -> InsBSTEQ(ins)
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Opcode.BSTEQ -> InsBSTEQ(ins)
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@ -656,6 +657,46 @@ class VirtualMachine(irProgram: IRProgram) {
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}
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}
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}
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}
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private fun InsRETURNI(i: IRInstruction) {
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if(callStack.isEmpty())
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exit(0)
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else {
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val context = callStack.removeLast()
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val returns = context.fcallSpec.returns
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when (i.type!!) {
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IRDataType.BYTE -> {
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if(returns.isNotEmpty())
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registers.setUB(returns.single().registerNum, i.immediate!!.toUByte())
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else {
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val callInstr = context.returnChunk.instructions[context.returnIndex-1]
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if(callInstr.opcode!=Opcode.CALL)
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throw IllegalArgumentException("missing return value reg")
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}
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}
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IRDataType.WORD -> {
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if(returns.isNotEmpty())
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registers.setUW(returns.single().registerNum, i.immediate!!.toUShort())
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else {
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val callInstr = context.returnChunk.instructions[context.returnIndex-1]
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if(callInstr.opcode!=Opcode.CALL)
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throw IllegalArgumentException("missing return value reg")
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}
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}
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IRDataType.FLOAT -> {
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if(returns.isNotEmpty())
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registers.setFloat(returns.single().registerNum, i.immediateFp!!)
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else {
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val callInstr = context.returnChunk.instructions[context.returnIndex-1]
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if(callInstr.opcode!=Opcode.CALL)
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throw IllegalArgumentException("missing return value reg")
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}
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}
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}
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pcChunk = context.returnChunk
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pcIndex = context.returnIndex
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}
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}
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private fun InsRETURNR(i: IRInstruction) {
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private fun InsRETURNR(i: IRInstruction) {
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if(callStack.isEmpty())
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if(callStack.isEmpty())
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exit(0)
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exit(0)
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