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https://github.com/irmen/prog8.git
synced 2024-06-25 15:29:45 +00:00
ir: EXT and EXTS opcodes now have 2 registers to avoid type clash
This commit is contained in:
Irmen de Jong
parent
e6b158bc97
commit
5037033fcf
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@ -167,15 +167,18 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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} else false
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if (assignment.value is PtMachineRegister) {
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valueRegister = (assignment.value as PtMachineRegister).register
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if(extendByteToWord)
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addInstr(result, IRInstruction(Opcode.EXT, IRDataType.BYTE, reg1=valueRegister), null)
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if(extendByteToWord) {
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valueRegister = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.EXT, IRDataType.BYTE, reg1=valueRegister, reg2=(assignment.value as PtMachineRegister).register), null)
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}
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} else {
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val tr = expressionEval.translateExpression(assignment.value)
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valueRegister = tr.resultReg
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addToResult(result, tr, valueRegister, -1)
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if(extendByteToWord) {
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valueRegister = codeGen.registers.nextFree()
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val opcode = if(assignment.value.type in SignedDatatypes) Opcode.EXTS else Opcode.EXT
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addInstr(result, IRInstruction(opcode, IRDataType.BYTE, reg1 = valueRegister), null)
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addInstr(result, IRInstruction(opcode, IRDataType.BYTE, reg1=valueRegister, reg2=tr.resultReg), null)
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}
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}
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}
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@ -172,10 +172,8 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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val compareReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADR, IRDataType.BYTE, reg1=compareReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.AND, IRDataType.BYTE, reg1=compareReg, immediate = 0x80)
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it += IRInstruction(Opcode.BEQ, IRDataType.BYTE, reg1=compareReg, immediate = 0, labelSymbol = notNegativeLabel)
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it += IRInstruction(Opcode.BSTPOS, labelSymbol = notNegativeLabel)
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it += IRInstruction(Opcode.NEG, IRDataType.BYTE, reg1=tr.resultReg)
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it += IRInstruction(Opcode.EXT, IRDataType.BYTE, reg1=tr.resultReg)
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}
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result += IRCodeChunk(notNegativeLabel, null)
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return ExpressionCodeResult(result, IRDataType.BYTE, tr.resultReg, -1)
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@ -185,8 +183,7 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe
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val compareReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADR, IRDataType.WORD, reg1=compareReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.AND, IRDataType.WORD, reg1=compareReg, immediate = 0x8000)
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it += IRInstruction(Opcode.BEQ, IRDataType.WORD, reg1=compareReg, immediate = 0, labelSymbol = notNegativeLabel)
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it += IRInstruction(Opcode.BSTPOS, labelSymbol = notNegativeLabel)
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it += IRInstruction(Opcode.NEG, IRDataType.WORD, reg1=tr.resultReg)
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}
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result += IRCodeChunk(notNegativeLabel, null)
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@ -274,13 +274,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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when(cast.value.type) {
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DataType.BYTE -> {
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// byte -> uword: sign extend
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actualResultReg2 = tr.resultReg
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addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg2), null)
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actualResultReg2 = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg2, reg2 = tr.resultReg), null)
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}
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DataType.UBYTE -> {
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// ubyte -> uword: sign extend
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actualResultReg2 = tr.resultReg
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addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2), null)
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actualResultReg2 = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2, reg2 = tr.resultReg), null)
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}
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DataType.WORD -> {
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actualResultReg2 = tr.resultReg
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@ -296,13 +296,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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when(cast.value.type) {
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DataType.BYTE -> {
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// byte -> word: sign extend
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actualResultReg2 = tr.resultReg
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addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg2), null)
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actualResultReg2 = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.EXTS, type = IRDataType.BYTE, reg1 = actualResultReg2, reg2=tr.resultReg), null)
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}
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DataType.UBYTE -> {
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// byte -> word: sign extend
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actualResultReg2 = tr.resultReg
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addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2), null)
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actualResultReg2 = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2, reg2=tr.resultReg), null)
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}
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DataType.UWORD -> {
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actualResultReg2 = tr.resultReg
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@ -2,7 +2,7 @@ TODO
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====
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- fix VM print_w
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- fix VM abs(byte) it always returns 0
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- fix VM abs(byte) it always returns 0 also check abs(word)
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- IR: instructions that do type conversion (SZ etc, CONCAT, SGN) should put the result in a DIFFERENT register.
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...
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@ -3,28 +3,13 @@
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%option no_sysinit
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main {
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sub set_color(ubyte dummy, uword arg) {
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arg++
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}
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sub start() {
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ubyte @shared current = cx16.screen_mode(0, true)
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ubyte @shared width
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ubyte @shared height
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txt.print_ub(current)
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txt.nl()
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cx16.set_screen_mode(128)
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%asm {{
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phx
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jsr cx16.get_screen_mode
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sta p8_current
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stx p8_width
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sty p8_height
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plx
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}}
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txt.print_ub(current)
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txt.spc()
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txt.print_ub(width)
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txt.spc()
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txt.print_ub(height)
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txt.nl()
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txt.nl()
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ubyte intens
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set_color(0, (intens >> 1) * $111)
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byte intensity = -25
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txt.print_b(intensity)
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@ -115,8 +115,8 @@ ARITHMETIC
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----------
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All have type b or w or f. Note: result types are the same as operand types! E.g. byte*byte->byte.
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exts reg1 - reg1 = signed extension of reg1 (byte to word, or word to long) (note: unlike M68k, exts.b -> word and exts.w -> long. The latter is not yet implemented yet as we don't have longs yet)
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ext reg1 - reg1 = unsigned extension of reg1 (which in practice just means clearing the MSB / MSW) (note: unlike M68k, ext.b -> word and ext.w -> long. The latter is not yet implemented yet as we don't have longs yet)
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exts reg1, reg2 - reg1 = signed extension of reg2 (byte to word, or word to long) (note: unlike M68k, exts.b -> word and exts.w -> long. The latter is not yet implemented yet as we don't have longs yet)
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ext reg1, reg2 - reg1 = unsigned extension of reg2 (which in practice just means clearing the MSB / MSW) (note: unlike M68k, ext.b -> word and ext.w -> long. The latter is not yet implemented yet as we don't have longs yet)
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inc reg1 - reg1 = reg1+1
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incm address - memory at address += 1
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dec reg1 - reg1 = reg1-1
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@ -583,8 +583,8 @@ val instructionFormats = mutableMapOf(
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Opcode.DIVMODR to InstructionFormat.from("BW,<>r1,<r2"),
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Opcode.DIVMOD to InstructionFormat.from("BW,<>r1,<i"),
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Opcode.CMP to InstructionFormat.from("BW,<r1,<r2"),
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Opcode.EXT to InstructionFormat.from("BW,<>r1"),
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Opcode.EXTS to InstructionFormat.from("BW,<>r1"),
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Opcode.EXT to InstructionFormat.from("BW,>r1,<r2"),
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Opcode.EXTS to InstructionFormat.from("BW,>r1,<r2"),
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Opcode.ANDR to InstructionFormat.from("BW,<>r1,<r2"),
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Opcode.AND to InstructionFormat.from("BW,<>r1,<i"),
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Opcode.ANDM to InstructionFormat.from("BW,<r1,<>a"),
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