From 54dd3a00df66a442e01095f5833715e7b41bd664 Mon Sep 17 00:00:00 2001 From: Irmen de Jong Date: Mon, 13 Mar 2023 03:20:06 +0100 Subject: [PATCH] refactor IR returnregs 3 --- .../codegen/intermediate/BuiltinFuncGen.kt | 49 ++-- .../codegen/intermediate/ExpressionGen.kt | 235 +++++++++--------- .../prog8/codegen/intermediate/IRCodeGen.kt | 69 +++-- docs/source/todo.rst | 2 + 4 files changed, 179 insertions(+), 176 deletions(-) diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt index b23bfc3b7..46e1b6741 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt @@ -109,15 +109,14 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe // TODO let all funcs return ExpressionCodeResult as well private fun funcCmp(call: PtBuiltinFunctionCall): IRCodeChunks { - val leftRegister = codeGen.registers.nextFree() - val rightRegister = codeGen.registers.nextFree() val result = mutableListOf() - var tr = exprGen.translateExpression(call.args[0]) - addToResult(result, tr, leftRegister, -1) - tr = exprGen.translateExpression(call.args[1]) - addToResult(result, tr, rightRegister, -1) + val leftTr = exprGen.translateExpression(call.args[0]) + addToResult(result, leftTr, leftTr.resultReg, -1) + val rightTr = exprGen.translateExpression(call.args[1]) + require(leftTr.resultReg!=rightTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) result += IRCodeChunk(null, null).also { - it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftRegister, reg2=rightRegister) + it += IRInstruction(Opcode.CMP, codeGen.irType(call.args[0].type), reg1=leftTr.resultReg, reg2=rightTr.resultReg) } return result } @@ -317,14 +316,14 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe } private fun funcMkword(call: PtBuiltinFunctionCall, resultRegister: Int): IRCodeChunks { - val msbReg = codeGen.registers.nextFree() val result = mutableListOf() - var tr = exprGen.translateExpression(call.args[0]) - addToResult(result, tr, msbReg, -1) - tr = exprGen.translateExpression(call.args[1]) - addToResult(result, tr, resultRegister, -1) + val msbTr = exprGen.translateExpression(call.args[0]) + addToResult(result, msbTr, msbTr.resultReg, -1) + val lsbTr = exprGen.translateExpression(call.args[1]) + require(lsbTr.resultReg!=msbTr.resultReg) + addToResult(result, lsbTr, resultRegister, -1) result += IRCodeChunk(null, null).also { - it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbReg) + it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = resultRegister, reg2 = msbTr.resultReg) } return result } @@ -355,13 +354,13 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe it += IRInstruction(Opcode.STOREM, IRDataType.WORD, reg1 = valueReg, value = address) } } else { - val addressReg = codeGen.registers.nextFree() - var tr = exprGen.translateExpression(call.args[0]) - addToResult(result, tr, addressReg, -1) - tr = exprGen.translateExpression(call.args[1]) - addToResult(result, tr, valueReg, -1) + val addressTr = exprGen.translateExpression(call.args[0]) + addToResult(result, addressTr, addressTr.resultReg, -1) + val valueTr = exprGen.translateExpression(call.args[1]) + require(valueTr.resultReg!=addressTr.resultReg) + addToResult(result, valueTr, valueReg, -1) result += IRCodeChunk(null, null).also { - it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressReg) + it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueReg, reg2 = addressTr.resultReg) } } } @@ -394,13 +393,13 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueReg, value = address) } } else { - val addressReg = codeGen.registers.nextFree() - var tr = exprGen.translateExpression(call.args[0]) - addToResult(result, tr, addressReg, -1) - tr = exprGen.translateExpression(call.args[1]) - addToResult(result, tr, valueReg, -1) + val addressTr = exprGen.translateExpression(call.args[0]) + addToResult(result, addressTr, addressTr.resultReg, -1) + val valueTr = exprGen.translateExpression(call.args[1]) + require(valueTr.resultReg!=addressTr.resultReg) + addToResult(result, valueTr, valueReg, -1) result += IRCodeChunk(null, null).also { - it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressReg) + it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueReg, reg2 = addressTr.resultReg) } } } diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt index 5e3aa0ade..43873efcd 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt @@ -459,10 +459,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null) } else { if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) { - var tr = translateExpression(binExpr.left) - addToResult(result, tr, SyscallRegisterBase, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, SyscallRegisterBase+1, -1) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, SyscallRegisterBase, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) if(resultRegister!=0) @@ -474,17 +475,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { IRInstruction(Opcode.SGTS, IRDataType.BYTE, reg1 = resultRegister, reg2 = 1) } } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) val ins = if (signed) { if (greaterEquals) Opcode.SGES else Opcode.SGTS } else { if (greaterEquals) Opcode.SGE else Opcode.SGT } - addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } } return result @@ -515,10 +516,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addInstr(result, IRInstruction(ins, IRDataType.BYTE, reg1 = resultRegister, reg2 = zeroRegister), null) } else { if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) { - var tr = translateExpression(binExpr.left) - addToResult(result, tr, SyscallRegisterBase, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, SyscallRegisterBase+1, -1) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, SyscallRegisterBase, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) if(resultRegister!=0) @@ -530,17 +532,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { IRInstruction(Opcode.SLTS, IRDataType.BYTE, reg1 = resultRegister, reg2 = 1) } } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) val ins = if (signed) { if (lessEquals) Opcode.SLES else Opcode.SLTS } else { if (lessEquals) Opcode.SLE else Opcode.SLT } - addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + addInstr(result, IRInstruction(ins, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } } return result @@ -567,10 +569,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { } } else { if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) { - var tr = translateExpression(binExpr.left) - addToResult(result, tr, SyscallRegisterBase, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, SyscallRegisterBase+1, -1) + val leftTr = translateExpression(binExpr.left) + addToResult(result, leftTr, SyscallRegisterBase, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) if(resultRegister!=0) @@ -586,13 +589,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val opcode = if (notEquals) Opcode.SNZ else Opcode.SZ addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = resultRegister), null) } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) val opcode = if (notEquals) Opcode.SNE else Opcode.SEQ - addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + addInstr(result, IRInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } } } @@ -607,13 +610,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val opc = if (signed) Opcode.ASR else Opcode.LSR addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister), null) } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) val opc = if (signed) Opcode.ASRN else Opcode.LSRN - addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + addInstr(result, IRInstruction(opc, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } return result } @@ -647,12 +650,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.LSL, vmDt, reg1=resultRegister), null) } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) - addInstr(result, IRInstruction(Opcode.LSLN, vmDt, reg1=resultRegister, rightResultReg), null) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.LSLN, vmDt, reg1=resultRegister, rightTr.resultReg), null) } return result } @@ -684,12 +687,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.XOR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) - addInstr(result, IRInstruction(Opcode.XORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.XORR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } return result } @@ -713,12 +716,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.AND, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr= translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) - addInstr(result, IRInstruction(Opcode.ANDR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + val leftTr = translateExpression(binExpr.left) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.ANDR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } return result } @@ -742,12 +745,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.OR, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) - addInstr(result, IRInstruction(Opcode.ORR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + val leftTr = translateExpression(binExpr.left) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.ORR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } return result } @@ -767,17 +770,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { private fun operatorModulo(binExpr: PtBinaryExpression, vmDt: IRDataType, resultRegister: Int): IRCodeChunks { require(vmDt!=IRDataType.FLOAT) {"floating-point modulo not supported ${binExpr.position}"} val result = mutableListOf() - val rightResultReg = codeGen.registers.nextFree() if(binExpr.right is PtNumber) { val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.MOD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) - addInstr(result, IRInstruction(Opcode.MODR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.MODR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } return result } @@ -796,15 +799,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val factor = constFactorRight.number.toFloat() result += codeGen.divideByConstFloat(resultFpRegister, factor) } else { - val rightResultFpReg = codeGen.registers.nextFreeFloat() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, -1, resultFpRegister) - tr = translateExpression(binExpr.right) - addToResult(result, tr, -1, rightResultFpReg) + val leftTr = translateExpression(binExpr.left) + addToResult(result, leftTr, -1, resultFpRegister) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultFpReg!=leftTr.resultFpReg) + addToResult(result, rightTr, -1, rightTr.resultFpReg) addInstr(result, if(signed) - IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg) + IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightTr.resultFpReg) else - IRInstruction(Opcode.DIVR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightResultFpReg) + IRInstruction(Opcode.DIVR, vmDt, fpReg1 = resultFpRegister, fpReg2=rightTr.resultFpReg) , null) } } else { @@ -814,7 +817,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val factor = constFactorRight.number.toInt() result += codeGen.divideByConst(vmDt, resultRegister, factor, signed) } else { - val rightResultReg = codeGen.registers.nextFree() if(binExpr.right is PtNumber) { val tr = translateExpression(binExpr.left) addToResult(result, tr, resultRegister, -1) @@ -824,14 +826,15 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { IRInstruction(Opcode.DIV, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()) , null) } else { - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) + val leftTr = translateExpression(binExpr.left) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, if (signed) - IRInstruction(Opcode.DIVSR, vmDt, reg1 = resultRegister, reg2 = rightResultReg) + IRInstruction(Opcode.DIVSR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg) else - IRInstruction(Opcode.DIVR, vmDt, reg1 = resultRegister, reg2 = rightResultReg) + IRInstruction(Opcode.DIVR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg) , null) } } @@ -904,12 +907,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val factor = constFactorRight.number.toFloat() result += codeGen.multiplyByConstFloat(resultFpRegister, factor) } else { - val rightResultFpReg = codeGen.registers.nextFreeFloat() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, -1, resultFpRegister) - tr = translateExpression(binExpr.right) - addToResult(result, tr, -1, rightResultFpReg) - addInstr(result, IRInstruction(Opcode.MULR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, -1, resultFpRegister) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultFpReg!=leftTr.resultFpReg) + addToResult(result, rightTr, -1, rightTr.resultFpReg) + addInstr(result, IRInstruction(Opcode.MULR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightTr.resultFpReg), null) } } else { if(constFactorLeft!=null && constFactorLeft.type!=DataType.FLOAT) { @@ -923,12 +926,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val factor = constFactorRight.number.toInt() result += codeGen.multiplyByConst(vmDt, resultRegister, factor) } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) - addInstr(result, IRInstruction(Opcode.MULR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.MULR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } } return result @@ -981,12 +984,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addToResult(result, tr, -1, resultFpRegister) addInstr(result, IRInstruction(Opcode.SUB, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null) } else { - val rightResultFpReg = codeGen.registers.nextFreeFloat() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, -1, resultFpRegister) - tr = translateExpression(binExpr.right) - addToResult(result, tr, -1, rightResultFpReg) - addInstr(result, IRInstruction(Opcode.SUBR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, -1, resultFpRegister) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultFpReg!=leftTr.resultFpReg) + addToResult(result, rightTr, -1, rightTr.resultFpReg) + addInstr(result, IRInstruction(Opcode.SUBR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightTr.resultFpReg), null) } } } else { @@ -1001,12 +1004,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.SUB, vmDt, reg1 = resultRegister, value = (binExpr.right as PtNumber).number.toInt()), null) } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) - addInstr(result, IRInstruction(Opcode.SUBR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.SUBR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } } } @@ -1072,12 +1075,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addToResult(result, tr, -1, resultFpRegister) addInstr(result, IRInstruction(Opcode.ADD, vmDt, fpReg1 = resultFpRegister, fpValue = (binExpr.right as PtNumber).number.toFloat()), null) } else { - val rightResultFpReg = codeGen.registers.nextFreeFloat() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, -1, resultFpRegister) - tr = translateExpression(binExpr.right) - addToResult(result, tr, -1, rightResultFpReg) - addInstr(result, IRInstruction(Opcode.ADDR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightResultFpReg), null) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, -1, resultFpRegister) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultFpReg!=leftTr.resultFpReg) + addToResult(result, rightTr, -1, rightTr.resultFpReg) + addInstr(result, IRInstruction(Opcode.ADDR, vmDt, fpReg1 = resultFpRegister, fpReg2 = rightTr.resultFpReg), null) } } } else { @@ -1097,12 +1100,12 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { addToResult(result, tr, resultRegister, -1) addInstr(result, IRInstruction(Opcode.ADD, vmDt, reg1 = resultRegister, value=(binExpr.right as PtNumber).number.toInt()), null) } else { - val rightResultReg = codeGen.registers.nextFree() - var tr = translateExpression(binExpr.left) - addToResult(result, tr, resultRegister, -1) - tr = translateExpression(binExpr.right) - addToResult(result, tr, rightResultReg, -1) - addInstr(result, IRInstruction(Opcode.ADDR, vmDt, reg1 = resultRegister, reg2 = rightResultReg), null) + val leftTr = translateExpression(binExpr.right) + addToResult(result, leftTr, resultRegister, -1) + val rightTr = translateExpression(binExpr.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) + addInstr(result, IRInstruction(Opcode.ADDR, vmDt, reg1 = resultRegister, reg2 = rightTr.resultReg), null) } } } diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt index 913d95086..ec6d2386f 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt @@ -517,8 +517,6 @@ class IRCodeGen( val step = iterable.step.number.toInt() if (step==0) throw AssemblyError("step 0") - val indexReg = registers.nextFree() - val endvalueReg = registers.nextFree() require(forLoop.variable.name == loopvar.scopedName) val loopvarSymbol = forLoop.variable.name val loopvarDt = when(loopvar) { @@ -530,22 +528,23 @@ class IRCodeGen( val loopLabel = createLabelName() val result = mutableListOf() - var tr = expressionEval.translateExpression(iterable.to) - addToResult(result, tr, endvalueReg, -1) - tr = expressionEval.translateExpression(iterable.from) - addToResult(result, tr, indexReg, -1) + val toTr = expressionEval.translateExpression(iterable.to) + addToResult(result, toTr, toTr.resultReg, -1) + val fromTr = expressionEval.translateExpression(iterable.from) + require(fromTr.resultReg!=toTr.resultReg) + addToResult(result, fromTr, fromTr.resultReg, -1) val labelAfterFor = createLabelName() val greaterOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGTS else Opcode.BGT - addInstr(result, IRInstruction(greaterOpcode, loopvarDtIr, indexReg, endvalueReg, labelSymbol=labelAfterFor), null) + addInstr(result, IRInstruction(greaterOpcode, loopvarDtIr, fromTr.resultReg, toTr.resultReg, labelSymbol=labelAfterFor), null) - addInstr(result, IRInstruction(Opcode.STOREM, loopvarDtIr, reg1=indexReg, labelSymbol=loopvarSymbol), null) + addInstr(result, IRInstruction(Opcode.STOREM, loopvarDtIr, reg1=fromTr.resultReg, labelSymbol=loopvarSymbol), null) result += labelFirstChunk(translateNode(forLoop.statements), loopLabel) result += addConstMem(loopvarDtIr, null, loopvarSymbol, step) - addInstr(result, IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = indexReg, labelSymbol = loopvarSymbol), null) + addInstr(result, IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = fromTr.resultReg, labelSymbol = loopvarSymbol), null) // if endvalue >= index, iterate loop val branchOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGES else Opcode.BGE - addInstr(result, IRInstruction(branchOpcode, loopvarDtIr, reg1=endvalueReg, reg2=indexReg, labelSymbol=loopLabel), null) + addInstr(result, IRInstruction(branchOpcode, loopvarDtIr, reg1=toTr.resultReg, reg2=fromTr.resultReg, labelSymbol=loopLabel), null) result += IRCodeChunk(labelAfterFor, null) return result @@ -918,6 +917,7 @@ class IRCodeGen( val leftTr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = expressionEval.translateExpression(ifElse.condition.right) + require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) result += IRCodeChunk(null,null).also { val compResultReg = registers.nextFree() @@ -942,6 +942,7 @@ class IRCodeGen( val leftTr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = expressionEval.translateExpression(ifElse.condition.right) + require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) val opcode: Opcode val firstReg: Int @@ -1060,14 +1061,13 @@ class IRCodeGen( val elseBranchSecondReg: Int val branchDt: IRDataType if(irDtLeft==IRDataType.FLOAT) { - val leftFpRegNum = registers.nextFreeFloat() - val rightFpRegNum = registers.nextFreeFloat() + val leftTr = expressionEval.translateExpression(ifElse.condition.left) + addToResult(result, leftTr, -1, leftTr.resultFpReg) + val rightTr = expressionEval.translateExpression(ifElse.condition.right) + require(rightTr.resultFpReg!=leftTr.resultFpReg) + addToResult(result, rightTr, -1, rightTr.resultFpReg) val compResultReg = registers.nextFree() - var tr = expressionEval.translateExpression(ifElse.condition.left) - addToResult(result, tr, -1, leftFpRegNum) - tr = expressionEval.translateExpression(ifElse.condition.right) - addToResult(result, tr, -1, rightFpRegNum) - addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftFpRegNum, fpReg2 = rightFpRegNum), null) + addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) val elseBranch = when (ifElse.condition.operator) { "==" -> Opcode.BNZ "!=" -> Opcode.BZ @@ -1096,46 +1096,45 @@ class IRCodeGen( } else { // integer comparisons branchDt = irDtLeft - val leftRegNum = registers.nextFree() - val rightRegNum = registers.nextFree() - var tr = expressionEval.translateExpression(ifElse.condition.left) - addToResult(result, tr, leftRegNum, -1) - tr = expressionEval.translateExpression(ifElse.condition.right) - addToResult(result, tr, rightRegNum, -1) + val leftTr = expressionEval.translateExpression(ifElse.condition.left) + addToResult(result, leftTr, leftTr.resultReg, -1) + val rightTr = expressionEval.translateExpression(ifElse.condition.right) + require(rightTr.resultReg!=leftTr.resultReg) + addToResult(result, rightTr, rightTr.resultReg, -1) when (ifElse.condition.operator) { "==" -> { elseBranchOpcode = Opcode.BNE - elseBranchFirstReg = leftRegNum - elseBranchSecondReg = rightRegNum + elseBranchFirstReg = leftTr.resultReg + elseBranchSecondReg = rightTr.resultReg } "!=" -> { elseBranchOpcode = Opcode.BEQ - elseBranchFirstReg = leftRegNum - elseBranchSecondReg = rightRegNum + elseBranchFirstReg = leftTr.resultReg + elseBranchSecondReg = rightTr.resultReg } "<" -> { // else part when left >= right elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE - elseBranchFirstReg = leftRegNum - elseBranchSecondReg = rightRegNum + elseBranchFirstReg = leftTr.resultReg + elseBranchSecondReg = rightTr.resultReg } ">" -> { // else part when left <= right --> right >= left elseBranchOpcode = if (signed) Opcode.BGES else Opcode.BGE - elseBranchFirstReg = rightRegNum - elseBranchSecondReg = leftRegNum + elseBranchFirstReg = rightTr.resultReg + elseBranchSecondReg = leftTr.resultReg } "<=" -> { // else part when left > right elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT - elseBranchFirstReg = leftRegNum - elseBranchSecondReg = rightRegNum + elseBranchFirstReg = leftTr.resultReg + elseBranchSecondReg = rightTr.resultReg } ">=" -> { // else part when left < right --> right > left elseBranchOpcode = if (signed) Opcode.BGTS else Opcode.BGT - elseBranchFirstReg = rightRegNum - elseBranchSecondReg = leftRegNum + elseBranchFirstReg = rightTr.resultReg + elseBranchSecondReg = leftTr.resultReg } else -> throw AssemblyError("invalid comparison operator") } diff --git a/docs/source/todo.rst b/docs/source/todo.rst index 3c4f86172..e2a8db39e 100644 --- a/docs/source/todo.rst +++ b/docs/source/todo.rst @@ -3,9 +3,11 @@ TODO For next minor release ^^^^^^^^^^^^^^^^^^^^^^ +- fix VM bsieve not printing the last number and string correctly - fix IR/VM crashing in bouncegfx and textelite - reduce the usage of register.nextFree() in IR codegen - get rid of ResultRegister in IR codegen? as the calls now encode this into the new opcodes... +- get rid of all the require() checks that test result regs to be different ...