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fix "fpReg1 out of bounds" crash for vm target for in-place float array assignment. #85

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Irmen de Jong
2022-10-29 17:04:39 +02:00
parent 6d6db70e42
commit 5b35232ab4
5 changed files with 28 additions and 11 deletions
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codeGenIntermediate/src/prog8/codegen/intermediate/AssignmentGen.kt
+1 -1
View File
@@ -239,7 +239,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
} else {
val indexReg = codeGen.registers.nextFree()
code += loadIndexReg(array, itemsize, indexReg, array.position)
code += IRInstruction(Opcode.STOREX, vmDt, reg1 = resultRegister, reg2=indexReg, labelSymbol = variable)
code += IRInstruction(Opcode.STOREX, vmDt, reg1 = indexReg, fpReg1 = resultFpRegister, labelSymbol = variable)
}
} else {
if(fixedIndex!=null) {
codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt
+7 -4
View File
@@ -58,7 +58,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
}
}
is PtTypeCast -> code += translate(expr, resultRegister, resultFpRegister)
is PtPrefix -> code += translate(expr, resultRegister)
is PtPrefix -> code += translate(expr, resultRegister, resultFpRegister)
is PtArrayIndexer -> code += translate(expr, resultRegister, resultFpRegister)
is PtBinaryExpression -> code += translate(expr, resultRegister, resultFpRegister)
is PtBuiltinFunctionCall -> code += codeGen.translateBuiltinFunc(expr, resultRegister)
@@ -139,14 +139,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
return code
}
private fun translate(expr: PtPrefix, resultRegister: Int): IRCodeChunk {
private fun translate(expr: PtPrefix, resultRegister: Int, resultFpRegister: Int): IRCodeChunk {
val code = IRCodeChunk(expr.position)
code += translateExpression(expr.value, resultRegister, -1)
code += translateExpression(expr.value, resultRegister, resultFpRegister)
val vmDt = codeGen.irType(expr.type)
when(expr.operator) {
"+" -> { }
"-" -> {
code += IRInstruction(Opcode.NEG, vmDt, reg1=resultRegister)
if(vmDt==IRDataType.FLOAT)
code += IRInstruction(Opcode.NEG, vmDt, fpReg1 = resultFpRegister)
else
code += IRInstruction(Opcode.NEG, vmDt, reg1 = resultRegister)
}
"~" -> {
val mask = if(vmDt==IRDataType.BYTE) 0x00ff else 0xffff