IR: remove broken loadi/storei optimization

docs/source/todo.rst

@@ -72,8 +72,6 @@ IR/VM
 - if instruction has both integer and float registers, the sequence of the registers is sometimes weird in the .p8ir file (float regs always at the end even when otherwise the target -integer- register is the first one in the list, for example.)
 - rollback this exception?:  "LOADI has an exception to allow reg1 and reg2 to be the same"  + actual exception check in the check "reg1 must not be same as reg2"
 - maybe change all branch instructions to have 2 exits (label if branch condition ture, and label if false) instead of 1, and get rid of the implicit "next code chunk" link between chunks.
-- in funcPoke() and funcPokemon(): switch address and value evaluation, to allow easier STOREI peephole optimization later
-- fix IR: TODO("peephole opt STOREI.float
 - if float<0 / if word<0  uses sgn or load, but still use a bgt etc instruction after that with a #0 operand even though the sgn and load instructions sets the status bits already, so just use bstneg etc
 - make multiple classes of registers and maybe also categorize by life time? , to prepare for better register allocation in the future
     SYSCALL_ARGS,        // Reserved for syscall arguments (r99000-99099, r99100-99199)
@@ -116,6 +114,8 @@ Libraries
 Optimizations
 -------------
 
+- optimize expression: uwordvar + 256  and variants.   (now uses 2 adds, can use 1 inc?)
+- optimize successive additions/subtractions and multiplications (with const) into just a single add/sub, mul
 - more optimized operator handling of different types, for example uword a ^ byte b now does a type cast of b to word first
 - optimize longEqualsValue() for long const and variable operands to not assign needlessly to R14-R15.
 - optimize optimizedBitwiseExpr()  for long const and variable operands to not assign needlessly to R14-R15.