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https://github.com/irmen/prog8.git
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vm: add in-place multiply
This commit is contained in:
Irmen de Jong
parent
461b6499ef
commit
5e4eb92443
@ -3,7 +3,6 @@ package prog8.codegen.virtual
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import prog8.code.ast.*
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import prog8.code.core.AssemblyError
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import prog8.code.core.DataType
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import prog8.code.core.Position
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import prog8.code.core.SignedDatatypes
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import prog8.vm.Opcode
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import prog8.vm.VmDataType
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@ -43,7 +42,7 @@ internal class AssignmentGen(private val codeGen: CodeGen, private val expressio
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}
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private fun assignSelfInMemory(
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targetAddress: Int,
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address: Int,
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value: PtExpression,
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origAssign: PtAssignment
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): VmCodeChunk {
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@ -52,15 +51,15 @@ internal class AssignmentGen(private val codeGen: CodeGen, private val expressio
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when(value) {
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is PtIdentifier -> return code // do nothing, x=x null assignment.
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is PtMachineRegister -> return code // do nothing, reg=reg null assignment
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is PtPrefix -> return inplacePrefix(value.operator, vmDt, targetAddress)
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is PtBinaryExpression -> return inplaceBinexpr(value.operator, value.right, vmDt, value.type in SignedDatatypes, targetAddress, origAssign)
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is PtPrefix -> return inplacePrefix(value.operator, vmDt, address)
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is PtBinaryExpression -> return inplaceBinexpr(value.operator, value.right, vmDt, value.type in SignedDatatypes, address, origAssign)
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is PtMemoryByte -> {
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return if (!codeGen.options.compTarget.machine.isIOAddress(targetAddress.toUInt()))
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return if (!codeGen.options.compTarget.machine.isIOAddress(address.toUInt()))
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code // do nothing, mem=mem null assignment.
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else {
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// read and write a (i/o) memory location to itself.
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code += VmCodeInstruction(Opcode.LOADM, vmDt, reg1 = 0, value = targetAddress)
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code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = 0, value = targetAddress)
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code += VmCodeInstruction(Opcode.LOADM, vmDt, reg1 = 0, value = address)
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code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = 0, value = address)
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code
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}
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}
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@ -77,16 +76,16 @@ internal class AssignmentGen(private val codeGen: CodeGen, private val expressio
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private fun inplaceBinexpr(
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operator: String,
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right: PtExpression,
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operand: PtExpression,
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vmDt: VmDataType,
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signed: Boolean,
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targetAddress: Int,
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address: Int,
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origAssign: PtAssignment
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): VmCodeChunk {
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when(operator) {
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"+" -> return expressionEval.operatorPlusInplace(targetAddress, vmDt, right)
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"-" -> return expressionEval.operatorMinusInplace(targetAddress, vmDt, right)
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"*" -> { /* TODO */ }
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"+" -> return expressionEval.operatorPlusInplace(address, vmDt, operand)
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"-" -> return expressionEval.operatorMinusInplace(address, vmDt, operand)
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"*" -> return expressionEval.operatorMultiplyInplace(address, vmDt, operand)
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"/" -> { /* TODO */ }
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"|" -> { /* TODO */ }
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"&" -> { /* TODO */ }
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@ -395,6 +395,20 @@ class CodeGen(internal val program: PtProgram,
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return code
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}
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internal fun multiplyByConstFloatInplace(address: Int, factor: Float): VmCodeChunk {
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val code = VmCodeChunk()
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if(factor==1f)
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return code
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if(factor==0f) {
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code += VmCodeInstruction(Opcode.STOREZM, VmDataType.FLOAT, value = address)
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} else {
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val factorReg = vmRegisters.nextFreeFloat()
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.FLOAT, fpReg1=factorReg, fpValue = factor)
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code += VmCodeInstruction(Opcode.MULM, VmDataType.FLOAT, fpReg1 = factorReg, value = address)
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}
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return code
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}
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internal val powersOfTwo = (0..16).map { 2.0.pow(it.toDouble()).toInt() }
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internal fun multiplyByConst(dt: VmDataType, reg: Int, factor: Int): VmCodeChunk {
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@ -424,6 +438,41 @@ class CodeGen(internal val program: PtProgram,
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return code
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}
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internal fun multiplyByConstInplace(dt: VmDataType, address: Int, factor: Int): VmCodeChunk {
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val code = VmCodeChunk()
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if(factor==1)
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return code
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val pow2 = powersOfTwo.indexOf(factor)
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if(pow2==1) {
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// just shift 1 bit
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// TODO use a memory shift instruction?
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val reg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=reg, value=address)
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code += VmCodeInstruction(Opcode.LSL, dt, reg1=reg)
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=reg, value=address)
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}
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else if(pow2>=1) {
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// just shift multiple bits
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// TODO use a memory shift instruction?
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val reg = vmRegisters.nextFree()
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val pow2reg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOADM, dt, reg1=reg, value=address)
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=pow2reg, value=pow2)
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code += VmCodeInstruction(Opcode.LSLN, dt, reg1=reg, reg2=pow2reg)
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code += VmCodeInstruction(Opcode.STOREM, dt, reg1=reg, value=address)
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} else {
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if (factor == 0) {
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code += VmCodeInstruction(Opcode.STOREZM, dt, value=address)
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}
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else {
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val factorReg = vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOAD, dt, reg1=factorReg, value = factor)
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code += VmCodeInstruction(Opcode.MULM, dt, reg1=factorReg, value = address)
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}
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}
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return code
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}
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internal fun divideByConstFloat(fpReg: Int, factor: Float): VmCodeChunk {
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val code = VmCodeChunk()
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if(factor==1f)
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@ -583,6 +583,31 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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return code
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}
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internal fun operatorMultiplyInplace(address: Int, vmDt: VmDataType, operand: PtExpression): VmCodeChunk {
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val code = VmCodeChunk()
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val constFactorRight = operand as? PtNumber
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if(vmDt==VmDataType.FLOAT) {
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if(constFactorRight!=null) {
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val factor = constFactorRight.number.toFloat()
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code += codeGen.multiplyByConstFloatInplace(address, factor)
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} else {
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val operandFpReg = codeGen.vmRegisters.nextFreeFloat()
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code += translateExpression(operand, -1, operandFpReg)
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code += VmCodeInstruction(Opcode.MULM, vmDt, fpReg1 = operandFpReg, value = address)
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}
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} else {
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if(constFactorRight!=null && constFactorRight.type!=DataType.FLOAT) {
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val factor = constFactorRight.number.toInt()
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code += codeGen.multiplyByConstInplace(vmDt, address, factor)
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} else {
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val operandReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(operand, operandReg, -1)
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code += VmCodeInstruction(Opcode.MULM, vmDt, reg1=operandReg, value = address)
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}
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}
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return code
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}
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private fun operatorMinus(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int, resultFpRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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if(vmDt==VmDataType.FLOAT) {
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@ -611,25 +636,25 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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return code
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}
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internal fun operatorMinusInplace(targetAddress: Int, vmDt: VmDataType, operand: PtExpression): VmCodeChunk {
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internal fun operatorMinusInplace(address: Int, vmDt: VmDataType, operand: PtExpression): VmCodeChunk {
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val code = VmCodeChunk()
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if(vmDt==VmDataType.FLOAT) {
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if((operand as? PtNumber)?.number==1.0) {
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code += VmCodeInstruction(Opcode.DECM, vmDt, value=targetAddress)
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code += VmCodeInstruction(Opcode.DECM, vmDt, value=address)
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}
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else {
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val operandFpReg = codeGen.vmRegisters.nextFreeFloat()
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code += translateExpression(operand, -1, operandFpReg)
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code += VmCodeInstruction(Opcode.SUBM, vmDt, fpReg1=operandFpReg, value=targetAddress)
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code += VmCodeInstruction(Opcode.SUBM, vmDt, fpReg1=operandFpReg, value=address)
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}
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} else {
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if((operand as? PtNumber)?.number==1.0) {
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code += VmCodeInstruction(Opcode.DECM, vmDt, value=targetAddress)
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code += VmCodeInstruction(Opcode.DECM, vmDt, value=address)
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}
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else {
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val operandReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(operand, operandReg, -1)
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code += VmCodeInstruction(Opcode.SUBM, vmDt, reg1=operandReg, value = targetAddress)
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code += VmCodeInstruction(Opcode.SUBM, vmDt, reg1=operandReg, value = address)
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}
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}
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return code
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@ -671,25 +696,25 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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return code
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}
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internal fun operatorPlusInplace(targetAddress: Int, vmDt: VmDataType, operand: PtExpression): VmCodeChunk {
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internal fun operatorPlusInplace(address: Int, vmDt: VmDataType, operand: PtExpression): VmCodeChunk {
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val code = VmCodeChunk()
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if(vmDt==VmDataType.FLOAT) {
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if((operand as? PtNumber)?.number==1.0) {
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code += VmCodeInstruction(Opcode.INCM, vmDt, value = targetAddress)
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code += VmCodeInstruction(Opcode.INCM, vmDt, value = address)
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}
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else {
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val operandFpReg = codeGen.vmRegisters.nextFreeFloat()
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code += translateExpression(operand, -1, operandFpReg)
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code += VmCodeInstruction(Opcode.ADDM, vmDt, fpReg1=operandFpReg, value=targetAddress)
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code += VmCodeInstruction(Opcode.ADDM, vmDt, fpReg1=operandFpReg, value=address)
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}
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} else {
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if((operand as? PtNumber)?.number==1.0) {
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code += VmCodeInstruction(Opcode.INCM, vmDt, value = targetAddress)
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code += VmCodeInstruction(Opcode.INCM, vmDt, value = address)
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}
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else {
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val operandReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(operand, operandReg, -1)
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code += VmCodeInstruction(Opcode.ADDM, vmDt, reg1=operandReg, value=targetAddress)
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code += VmCodeInstruction(Opcode.ADDM, vmDt, reg1=operandReg, value=address)
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}
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}
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return code
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@ -98,9 +98,13 @@ negm address - sign negate memory at address
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add reg1, reg2 - reg1 += reg2 (unsigned + signed)
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addm reg1, address - memory at address += reg1 (unsigned + signed)
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sub reg1, reg2 - reg1 -= reg2 (unsigned + signed)
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subm reg1, address - memory at address -= reg2 (unsigned + signed)
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mul reg1, reg2 - unsigned multiply reg1 *= reg2 note: byte*byte->byte, no type extension to word!
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mulm reg1, address - memory at address *= reg2 note: byte*byte->byte, no type extension to word!
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div reg1, reg2 - unsigned division reg1 /= reg2 note: division by zero yields max int $ff/$ffff
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divm reg1, address - memory at address /= reg2 note: division by zero yields max int $ff/$ffff
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divs reg1, reg2 - signed division reg1 /= reg2 note: division by zero yields max signed int 127 / 32767
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divsm reg1, address - signed memory at address /= reg2 note: division by zero yields max signed int 127 / 32767
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mod reg1, reg2 - remainder (modulo) of unsigned division reg1 %= reg2 note: division by zero yields max signed int $ff/$ffff
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sqrt reg1, reg2 - reg1 is the square root of reg2
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sgn reg1, reg2 - reg1 is the sign of reg2 (0, 1 or -1)
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@ -131,6 +135,8 @@ roxr reg1 - rotate reg1 right by 1 bits, usin
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rol reg1 - rotate reg1 left by 1 bits, not using carry + set Carry to shifted bit
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roxl reg1 - rotate reg1 left by 1 bits, using carry, + set Carry to shifted bit
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TODO: add memory-shift instructions?
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FLOATING POINT CONVERSIONS AND FUNCTIONS
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----------------------------------------
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@ -291,6 +297,11 @@ val OpcodesWithAddress = setOf(
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Opcode.INCM,
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Opcode.DECM,
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Opcode.NEGM,
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Opcode.ADDM,
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Opcode.SUBM,
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Opcode.MULM,
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Opcode.DIVM,
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Opcode.DIVSM,
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Opcode.NOTM,
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Opcode.XORM
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)
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@ -142,7 +142,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.SUB -> InsSUB(ins)
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Opcode.SUBM -> InsSUBM(ins)
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Opcode.MUL -> InsMUL(ins)
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Opcode.MULM -> TODO()
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Opcode.MULM -> InsMULM(ins)
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Opcode.DIV -> InsDIV(ins)
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Opcode.DIVM -> TODO()
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Opcode.DIVS -> InsDIVS(ins)
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@ -735,6 +735,21 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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}
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private fun InsMULM(i: Instruction) {
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val address = i.value!!
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when(i.type!!) {
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VmDataType.BYTE -> plusMinusMultAnyByteInplace("*", i.reg1!!, address)
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VmDataType.WORD -> plusMinusMultAnyWordInplace("*", i.reg1!!, address)
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VmDataType.FLOAT -> {
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val left = memory.getFloat(address)
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val right = registers.getFloat(i.fpReg1!!)
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val result = arithFloat(left, "*", right)
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memory.setFloat(address, result)
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}
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}
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pc++
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}
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private fun InsDIV(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> divModByteUnsigned("/", i.reg1!!, i.reg2!!)
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