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https://github.com/irmen/prog8.git
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IR: fix romsub encoding
This commit is contained in:
Irmen de Jong
parent
905921a684
commit
630c8a5faa
@ -235,7 +235,7 @@ class StSub(name: String, val parameters: List<StSubroutineParameter>, val retur
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class StRomSub(name: String,
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val address: UInt,
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val address: UInt?, // null in case of asmsub, specified in case of romsub
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val parameters: List<StRomSubParameter>,
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val returns: List<StRomSubParameter>,
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astNode: PtNode) :
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@ -40,14 +40,9 @@ class SymbolTableMaker(private val program: PtProgram, private val options: Comp
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private fun addToSt(node: PtNode, scope: Stack<StNode>) {
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val stNode = when(node) {
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is PtAsmSub -> {
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if(node.address==null) {
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val params = node.parameters.map { StSubroutineParameter(it.second.name, it.second.type) }
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StSub(node.name, params, node.returns.singleOrNull()?.second, node)
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} else {
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val parameters = node.parameters.map { StRomSubParameter(it.first, it.second.type) }
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val returns = node.returns.map { StRomSubParameter(it.first, it.second) }
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StRomSub(node.name, node.address, parameters, returns, node)
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}
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val parameters = node.parameters.map { StRomSubParameter(it.first, it.second.type) }
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val returns = node.returns.map { StRomSubParameter(it.first, it.second) }
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StRomSub(node.name, node.address, parameters, returns, node)
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}
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is PtBlock -> {
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StNode(node.name, StNodeType.BLOCK, node)
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@ -4,7 +4,10 @@ import prog8.code.StRomSub
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import prog8.code.StStaticVariable
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import prog8.code.StSub
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import prog8.code.ast.*
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import prog8.code.core.*
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import prog8.code.core.AssemblyError
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import prog8.code.core.DataType
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import prog8.code.core.PassByValueDatatypes
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import prog8.code.core.SignedDatatypes
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import prog8.intermediate.*
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internal class ExpressionCodeResult(val chunks: IRCodeChunks, val dt: IRDataType, val resultReg: Int, val resultFpReg: Int) {
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@ -361,10 +364,10 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addInstr(result, call, null)
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return if(fcall.void)
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ExpressionCodeResult(result, IRDataType.BYTE, -1, -1)
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else if(call.fcallArgs!!.returns!!.dt==IRDataType.FLOAT)
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ExpressionCodeResult(result, codeGen.irType(fcall.type), -1, call.fcallArgs!!.returns!!.registerNum)
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else if(fcall.type==DataType.FLOAT)
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ExpressionCodeResult(result, returnRegSpec!!.dt, -1, returnRegSpec.registerNum)
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else
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ExpressionCodeResult(result, codeGen.irType(fcall.type), call.fcallArgs!!.returns!!.registerNum, -1)
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ExpressionCodeResult(result, returnRegSpec!!.dt, returnRegSpec.registerNum, -1)
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}
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is StRomSub -> {
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val result = mutableListOf<IRCodeChunkBase>()
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@ -401,30 +404,18 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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}
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// create the call
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val call = IRInstruction(Opcode.CALL, address = callTarget.address.toInt(), fcallArgs = FunctionCallArgs(argRegisters, returnRegSpec))
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val call =
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if(callTarget.address==null)
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IRInstruction(Opcode.CALL, labelSymbol = fcall.name, fcallArgs = FunctionCallArgs(argRegisters, returnRegSpec))
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else
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IRInstruction(Opcode.CALL, address = callTarget.address!!.toInt(), fcallArgs = FunctionCallArgs(argRegisters, returnRegSpec))
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addInstr(result, call, null)
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if(fcall.void) {
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return ExpressionCodeResult(result, IRDataType.BYTE, -1, -1)
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} else {
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val regStr = if(callTarget.returns.isEmpty())
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throw AssemblyError("expect a return value")
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else if(callTarget.returns.size==1) {
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val returns = callTarget.returns.single()
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if(returns.register.registerOrPair!=null) returns.register.registerOrPair.toString() else returns.register.statusflag.toString()
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} else {
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// multiple return values: take the first *register* (not status flag) return value and ignore the rest.
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callTarget.returns.first { it.register.registerOrPair!=null }.toString()
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}
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return if(fcall.type==DataType.FLOAT) {
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val resultFpReg = codeGen.registers.nextFreeFloat()
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addInstr(result, IRInstruction(Opcode.LOADCPU, IRDataType.FLOAT, fpReg1 = resultFpReg, labelSymbol = regStr), null)
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ExpressionCodeResult(result, returnRegSpec!!.dt, -1, resultFpReg)
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} else {
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val resultReg = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.LOADCPU, returnRegSpec!!.dt, reg1 = resultReg, labelSymbol = regStr), null)
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ExpressionCodeResult(result, returnRegSpec.dt, resultReg, -1)
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}
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}
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return if(fcall.void)
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ExpressionCodeResult(result, IRDataType.BYTE, -1, -1)
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else if(fcall.type==DataType.FLOAT)
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ExpressionCodeResult(result, returnRegSpec!!.dt, -1, returnRegSpec.registerNum)
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else
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ExpressionCodeResult(result, returnRegSpec!!.dt, returnRegSpec.registerNum, -1)
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}
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else -> throw AssemblyError("invalid node type")
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}
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@ -3,7 +3,7 @@ TODO
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For next minor release
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^^^^^^^^^^^^^^^^^^^^^^
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- fix VM problem with param passing: void string.copy(".prg", &output_filename + string.length(output_filename))
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- fix romsub encoding into IR
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...
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@ -1,27 +1,15 @@
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%import textio
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%import string
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%zeropage basicsafe
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main {
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sub start() {
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txt.chrout('!')
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txt.print("test")
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txt.nl()
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; uword seconds_uword = 1
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; uword remainder = seconds_uword % $0003 ==0
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; txt.print_uw(remainder)
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;
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; blerp()
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ubyte @shared foo = derp(99)
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}
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sub blerp() {
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%ir {{
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_xxx:
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loadr r2,r3
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_yyy:
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loadr r3,r4
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return
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asmsub derp(ubyte xx @Y) -> ubyte @ A {
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%asm {{
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rts
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}}
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}
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}
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@ -1,6 +1,5 @@
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package prog8.intermediate
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import prog8.code.core.CpuRegister
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import prog8.code.core.RegisterOrStatusflag
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import prog8.code.core.toHex
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@ -39,15 +38,11 @@ loadi reg1, reg2 - load reg1 with value at memory indirect,
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loadx reg1, reg2, address - load reg1 with value at memory address indexed by value in reg2
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loadix reg1, reg2, pointeraddr - load reg1 with value at memory indirect, pointed to by pointeraddr indexed by value in reg2
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loadr reg1, reg2 - load reg1 with value in register reg2
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loadcpu reg1, cpureg - load reg1 with value from cpu register (register/registerpair/statusflag)
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storem reg1, address - store reg1 at memory address
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storecpu reg1, cpureg - store reg1 in cpu register (register/registerpair/statusflag)
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storei reg1, reg2 - store reg1 at memory indirect, memory pointed to by reg2
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storex reg1, reg2, address - store reg1 at memory address, indexed by value in reg2
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storeix reg1, reg2, pointeraddr - store reg1 at memory indirect, pointed to by pointeraddr indexed by value in reg2
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storezm address - store zero at memory address
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storezcpu cpureg - store zero in cpu register (register/registerpair/statusflag)
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storezi reg1 - store zero at memory pointed to by reg1
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storezx reg1, address - store zero at memory address, indexed by value in reg
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@ -60,6 +55,9 @@ call label(argument register list) [: resultreg.type]
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- calls a subroutine with the given arguments and return value (optional).
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save current instruction location+1, continue execution at instruction nr of the label.
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the argument register list is positional and includes the datatype, ex.: r4.b,r5.w,fp1.f
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If the call is to a rom-routine, 'label' will be a hexadecimal address instead such as $ffd2
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If the arguments should be passed in CPU registers, they'll have a @REGISTER postfix.
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For example: call $ffd2(r5.b@A)
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syscall number (argument register list) [: resultreg.type]
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- do a systemcall identified by number, result value(s) are pushed on value stack by the syscall code so
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will be POPped off into the given resultregister if any.
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@ -231,9 +229,7 @@ enum class Opcode {
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LOADX,
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LOADIX,
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LOADR,
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LOADCPU,
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STOREM,
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STORECPU,
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STOREI,
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STOREX,
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STOREIX,
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@ -418,11 +414,6 @@ val OpcodesThatBranch = setOf(
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Opcode.BLES
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)
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val OpcodesForCpuRegisters = setOf(
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Opcode.LOADCPU,
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Opcode.STORECPU
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)
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enum class IRDataType {
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BYTE,
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WORD,
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@ -513,9 +504,7 @@ val instructionFormats = mutableMapOf(
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Opcode.LOADX to InstructionFormat.from("BW,>r1,<r2,<a | F,>fr1,<r1,<a"),
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Opcode.LOADIX to InstructionFormat.from("BW,>r1,<r2,<a | F,>fr1,<r1,<a"),
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Opcode.LOADR to InstructionFormat.from("BW,>r1,<r2 | F,>fr1,<fr2"),
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Opcode.LOADCPU to InstructionFormat.from("BW,>r1"),
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Opcode.STOREM to InstructionFormat.from("BW,<r1,>a | F,<fr1,>a"),
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Opcode.STORECPU to InstructionFormat.from("BW,<r1"),
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Opcode.STOREI to InstructionFormat.from("BW,<r1,<r2 | F,<fr1,<r1"),
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Opcode.STOREX to InstructionFormat.from("BW,<r1,<r2,>a | F,<fr1,<r1,>a"),
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Opcode.STOREIX to InstructionFormat.from("BW,<r1,<r2,>a | F,<fr1,<r1,>a"),
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@ -823,33 +812,47 @@ data class IRInstruction(
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}
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if(this.fcallArgs!=null) {
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immediate?.let { result.add(it.toHex()) }
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labelSymbol?.let { result.add(it) }
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immediate?.let { result.add(it.toHex()) } // syscall
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labelSymbol?.let { result.add(it) } // regular subroutine call
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address?.let { result.add(address.toHex()) } // romcall
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result.add("(")
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fcallArgs.arguments.forEach {
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val location = if(it.address==null) {
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if(it.name.isBlank()) "" else it.name+"="
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} else "${it.address}="
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if(it.reg.cpuRegister!=null)
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TODO("handle cpuregister ${it.reg.cpuRegister}")
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val cpuReg = if(it.reg.cpuRegister==null) "" else {
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if(it.reg.cpuRegister.registerOrPair!=null)
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"@"+it.reg.cpuRegister.registerOrPair.toString()
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else
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"@"+it.reg.cpuRegister.statusflag.toString()
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}
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when(it.reg.dt) {
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IRDataType.BYTE -> result.add("${location}r${it.reg.registerNum}.b,")
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IRDataType.WORD -> result.add("${location}r${it.reg.registerNum}.w,")
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IRDataType.FLOAT -> result.add("${location}fr${it.reg.registerNum}.f,")
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IRDataType.BYTE -> result.add("${location}r${it.reg.registerNum}.b$cpuReg,")
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IRDataType.WORD -> result.add("${location}r${it.reg.registerNum}.w$cpuReg,")
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IRDataType.FLOAT -> result.add("${location}fr${it.reg.registerNum}.f$cpuReg,")
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}
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}
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if(result.last().endsWith(',')) {
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result.add(result.removeLast().trimEnd(','))
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}
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result.add(")")
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fcallArgs.returns?.let {
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val returns = fcallArgs.returns
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if(returns!=null) {
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result.add(":")
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when(it.dt) {
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IRDataType.BYTE -> result.add("r${it.registerNum}.b")
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IRDataType.WORD -> result.add("r${it.registerNum}.w")
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IRDataType.FLOAT -> result.add("fr${it.registerNum}.f")
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when (returns.dt) {
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IRDataType.BYTE -> result.add("r${returns.registerNum}.b")
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IRDataType.WORD -> result.add("r${returns.registerNum}.w")
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IRDataType.FLOAT -> result.add("fr${returns.registerNum}.f")
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}
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if(returns.cpuRegister!=null) {
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val cpuReg =
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if(returns.cpuRegister.registerOrPair!=null)
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returns.cpuRegister.registerOrPair.toString()
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else
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returns.cpuRegister.statusflag.toString()
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result.add("@"+cpuReg)
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}
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}
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} else {
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@ -211,21 +211,6 @@ fun parseIRCodeLine(line: String): Either<IRInstruction, String> {
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throw IRParseException("labelsymbol confused with register?: $labelSymbol")
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}
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if(opcode in OpcodesForCpuRegisters) {
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val reg = operands.last().lowercase()
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if(reg !in setOf(
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"a", "x", "y",
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"ax", "ay", "xy",
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"r0", "r1", "r2", "r3",
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"r4", "r5", "r6", "r7",
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"r8", "r9", "r10","r11",
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"r12", "r13", "r14", "r15",
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"pc", "pz", "pv","pn"))
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throw IRParseException("invalid cpu reg: $reg")
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return left(IRInstruction(opcode, type, reg1, labelSymbol = reg))
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}
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return left(IRInstruction(opcode, type, reg1, reg2, fpReg1, fpReg2, immediateInt, immediateFp, address, labelSymbol = labelSymbol))
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}
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@ -283,8 +283,6 @@ class VirtualMachine(irProgram: IRProgram) {
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Opcode.BREAKPOINT -> InsBREAKPOINT()
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Opcode.CLC -> { statusCarry = false; nextPc() }
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Opcode.SEC -> { statusCarry = true; nextPc() }
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Opcode.LOADCPU -> InsLOADCPU(ins)
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Opcode.STORECPU -> InsSTORECPU(ins)
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Opcode.FFROMUB -> InsFFROMUB(ins)
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Opcode.FFROMSB -> InsFFROMSB(ins)
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@ -373,81 +371,6 @@ class VirtualMachine(irProgram: IRProgram) {
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throw BreakpointException(pcChunk, pcIndex)
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}
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private fun InsLOADCPU(i: IRInstruction) {
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val reg = i.labelSymbol!!
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val value: UInt
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if(reg.startsWith('r')) {
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val regnum = reg.substring(1).toInt()
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val regAddr = cx16virtualregsBaseAddress + regnum*2
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value = memory.getUW(regAddr).toUInt()
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} else {
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value = when(reg) {
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"a" -> registers.cpuA.toUInt()
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"x" -> registers.cpuX.toUInt()
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"y" -> registers.cpuY.toUInt()
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"ax" -> (registers.cpuA.toUInt() shl 8) or registers.cpuX.toUInt()
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"ay" -> (registers.cpuA.toUInt() shl 8) or registers.cpuY.toUInt()
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"xy" -> (registers.cpuX.toUInt() shl 8) or registers.cpuY.toUInt()
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"pc" -> if(statusCarry) 1u else 0u
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"pz" -> if(statusZero) 1u else 0u
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"pn" -> if(statusNegative) 1u else 0u
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"pv" -> throw IllegalArgumentException("overflow status register not supported in VM")
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else -> throw IllegalArgumentException("invalid cpu reg")
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}
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}
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when(i.type!!) {
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IRDataType.BYTE -> registers.setUB(i.reg1!!, value.toUByte())
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IRDataType.WORD -> registers.setUW(i.reg1!!, value.toUShort())
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else -> throw java.lang.IllegalArgumentException("invalid cpu reg type")
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}
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nextPc()
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}
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private fun InsSTORECPU(i: IRInstruction) {
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val value: UInt = when(i.type!!) {
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IRDataType.BYTE -> registers.getUB(i.reg1!!).toUInt()
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IRDataType.WORD -> registers.getUW(i.reg1!!).toUInt()
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IRDataType.FLOAT -> throw IllegalArgumentException("there are no float cpu registers")
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}
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StoreCPU(value, i.type!!, i.labelSymbol!!)
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nextPc()
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}
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private fun StoreCPU(value: UInt, dt: IRDataType, regStr: String) {
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if(regStr.startsWith('r')) {
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val regnum = regStr.substring(1).toInt()
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val regAddr = cx16virtualregsBaseAddress + regnum*2
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when(dt) {
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IRDataType.BYTE -> memory.setUB(regAddr, value.toUByte())
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IRDataType.WORD -> memory.setUW(regAddr, value.toUShort())
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else -> throw IllegalArgumentException("invalid reg dt")
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}
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} else {
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when (regStr) {
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"a" -> registers.cpuA = value.toUByte()
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"x" -> registers.cpuX = value.toUByte()
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"y" -> registers.cpuY = value.toUByte()
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"ax" -> {
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registers.cpuA = (value and 255u).toUByte()
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registers.cpuX = (value shr 8).toUByte()
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}
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"ay" -> {
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registers.cpuA = (value and 255u).toUByte()
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registers.cpuY = (value shr 8).toUByte()
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}
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"xy" -> {
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registers.cpuX = (value and 255u).toUByte()
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registers.cpuY = (value shr 8).toUByte()
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}
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"pc" -> statusCarry = value == 1u
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"pz" -> statusZero = value == 1u
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"pn" -> statusNegative = value == 1u
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"pv" -> throw IllegalArgumentException("overflow status register not supported in VM")
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else -> throw IllegalArgumentException("invalid cpu reg")
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}
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}
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}
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private fun InsLOAD(i: IRInstruction) {
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if(i.type==IRDataType.FLOAT)
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registers.setFloat(i.fpReg1!!, i.immediateFp!!)
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@ -67,7 +67,7 @@ class VmProgramLoader {
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programChunks.forEach {
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it.instructions.forEach { ins ->
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if (ins.labelSymbol != null && ins.opcode !in OpcodesThatBranch && ins.opcode !in OpcodesForCpuRegisters)
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if (ins.labelSymbol != null && ins.opcode !in OpcodesThatBranch)
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require(ins.address != null) { "instruction with labelSymbol for a var should have value set to the memory address" }
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}
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}
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@ -152,16 +152,12 @@ class VmProgramLoader {
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// placeholder is not a variable, so it must be a label of a code chunk instead
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val target: IRCodeChunk? = chunks.firstOrNull { it.label==label }
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val opcode = chunk.instructions[line].opcode
|
||||
if(target==null) {
|
||||
// exception allowed: storecpu/loadcpu instructions that refer to CPU registers
|
||||
if(opcode !in OpcodesForCpuRegisters)
|
||||
throw IRParseException("placeholder not found in variables nor labels: $label")
|
||||
}
|
||||
else if(opcode in OpcodesThatBranch) {
|
||||
if(target==null)
|
||||
throw IRParseException("placeholder not found in variables nor labels: $label")
|
||||
else if(opcode in OpcodesThatBranch)
|
||||
chunk.instructions[line] = chunk.instructions[line].copy(branchTarget = target, address = null)
|
||||
} else {
|
||||
else
|
||||
throw IRParseException("vm cannot yet load a label address as a value: ${chunk.instructions[line]}") // TODO
|
||||
}
|
||||
}
|
||||
} else {
|
||||
chunk.instructions[line] = chunk.instructions[line].copy(address = replacement)
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user