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fix cx16.r0 base address to be $04 on the C-64, and fix zeropage duplicate free addresses

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This commit is contained in:
Irmen de Jong 2022-08-12 17:27:58 +02:00
parent 44ee4b989f
commit 666d62dd7a
5 changed files with 18 additions and 1 deletions
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4
codeCore/src/prog8/code/target/atari/AtariZeropage.kt
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@ -39,6 +39,10 @@ class AtariZeropage(options: CompilationOptions) : Zeropage(options) {
}
}
val distictFree = free.distinct()
free.clear()
free.addAll(distictFree)
removeReservedFromFreePool()
}

4
codeCore/src/prog8/code/target/c128/C128Zeropage.kt
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@ -38,6 +38,10 @@ class C128Zeropage(options: CompilationOptions) : Zeropage(options) {
}
}
val distictFree = free.distinct()
free.clear()
free.addAll(distictFree)
removeReservedFromFreePool()
}

5
codeCore/src/prog8/code/target/c64/C64Zeropage.kt
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@ -65,6 +65,10 @@ class C64Zeropage(options: CompilationOptions) : Zeropage(options) {
}
}
val distictFree = free.distinct()
free.clear()
free.addAll(distictFree)
removeReservedFromFreePool()
if(options.zeropage==ZeropageType.FULL || options.zeropage==ZeropageType.KERNALSAFE) {
@ -77,6 +81,7 @@ class C64Zeropage(options: CompilationOptions) : Zeropage(options) {
// Note: the 16 virtual registers R0-R15 are not regular allocated variables, they're *memory mapped* elsewhere to fixed addresses.
// However, to be able for the compiler to "see" them as zero page variables, we have to register them here as well.
// This is important because the compiler sometimes treats ZP variables more efficiently (for example if it's a pointer)
// The base addres is $04. Unfortunately it cannot be the same as on the Commander X16 ($02).
for(reg in 0..15) {
allocatedVariables[listOf("cx16", "r${reg}")] = ZpAllocation((4+reg*2).toUInt(), DataType.UWORD, 2) // cx16.r0 .. cx16.r15
allocatedVariables[listOf("cx16", "r${reg}s")] = ZpAllocation((4+reg*2).toUInt(), DataType.WORD, 2) // cx16.r0s .. cx16.r15s

4
codeCore/src/prog8/code/target/cx16/CX16Zeropage.kt
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@ -43,6 +43,10 @@ class CX16Zeropage(options: CompilationOptions) : Zeropage(options) {
else -> throw InternalCompilerException("for this machine target, zero page type 'floatsafe' is not available. ${options.zeropage}")
}
val distictFree = free.distinct()
free.clear()
free.addAll(distictFree)
removeReservedFromFreePool()
allocateCx16VirtualRegisters()

2
compiler/src/prog8/compiler/astprocessing/AstPreprocessor.kt
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@ -21,7 +21,7 @@ class AstPreprocessor(val program: Program,
override fun before(program: Program): Iterable<IAstModification> {
if(options.compTarget.name==C64Target.NAME) {
relocateCx16VirtualRegisters(program, 0x0002u) // same address as CommanderX16
relocateCx16VirtualRegisters(program, 0x0004u) // unfortunately, can't be the same address as CommanderX16
}
else if(options.compTarget.name!=Cx16Target.NAME) {
relocateCx16VirtualRegisters(program, options.compTarget.machine.ESTACK_HI)