mirror of
https://github.com/irmen/prog8.git
synced 2025-02-19 11:31:07 +00:00
optimize monogfx.plot() to use a *40 lookup table in lores mode. Speeds up a lot of other routines too (line etc)
This commit is contained in:
Irmen de Jong
parent
f2cfcfdf31
commit
68d5983a14
@ -16,6 +16,7 @@ monogfx {
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; read-only control variables:
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uword width = 0
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uword height = 0
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bool lores_mode
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ubyte mode
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const ubyte MODE_NORMAL = %00000000
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const ubyte MODE_STIPPLE = %00000001
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@ -32,6 +33,7 @@ monogfx {
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cx16.VERA_L1_TILEBASE = 0
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width = 320
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height = 240
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lores_mode = true
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mode = MODE_NORMAL
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clear_screen(false)
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}
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@ -47,6 +49,7 @@ monogfx {
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cx16.VERA_L1_TILEBASE = %00000001
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width = 640
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height = 480
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lores_mode = false
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mode = MODE_NORMAL
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clear_screen(false)
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}
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@ -64,15 +67,12 @@ monogfx {
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sub clear_screen(bool draw) {
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position(0, 0)
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when width {
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320 -> {
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repeat 240/2/8
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cs_innerloop640(draw)
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}
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640 -> {
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repeat 480/8
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cs_innerloop640(draw)
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}
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if lores_mode {
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repeat 240/2/8
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cs_innerloop640(draw)
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} else {
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repeat 480/8
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cs_innerloop640(draw)
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}
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position(0, 0)
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}
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@ -109,7 +109,7 @@ monogfx {
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return
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if length<=8 {
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; just use 2 byte writes with shifted mask
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position2(xx,yy,true)
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position2(xx,yy)
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%asm {{
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ldy p8v_length
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lda p8v_masked_ends,y
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@ -309,8 +309,8 @@ _done
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}}
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if mode!=MODE_STIPPLE {
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; draw continuous line.
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position2(xx,yy,true)
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if width==320
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position2(xx,yy)
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if lores_mode
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set_both_strides(11) ; 40 increment = 1 line in 320 px monochrome
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else
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set_both_strides(12) ; 80 increment = 1 line in 640 px monochrome
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@ -328,8 +328,8 @@ drawmode: ora cx16.r15L
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lheight--
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}
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lheight++ ; because it is divided by 2 later, don't round off the last pixel
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position2(xx,yy,true)
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if width==320
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position2(xx,yy)
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if lores_mode
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set_both_strides(12) ; 80 increment = 2 line in 320 px monochrome
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else
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set_both_strides(13) ; 160 increment = 2 line in 640 px monochrome
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@ -342,9 +342,9 @@ drawmode: ora cx16.r15L
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}
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}
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} else {
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position2(xx,yy,true)
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position2(xx,yy)
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cx16.r15 = ~cx16.r15 ; erase pixels
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if width==320
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if lores_mode
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set_both_strides(11) ; 40 increment = 1 line in 320 px monochrome
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else
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set_both_strides(12) ; 80 increment = 1 line in 640 px monochrome
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@ -679,26 +679,51 @@ invert:
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return
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sub prepare() {
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%asm {{
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lda p8v_xx
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and #7
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pha ; xbits
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}}
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xx /= 8
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if width==320
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xx += yy*(320/8) ; TODO *40 table
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else
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xx += yy*(640/8) ; TODO *80 table? (a bit large, need lo,mid,hi. maybe just reuse *40 table and do 1 shift.)
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%asm {{
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stz cx16.VERA_CTRL
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stz cx16.VERA_ADDR_H
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lda p8v_xx+1
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sta cx16.VERA_ADDR_M
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lda p8v_xx
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sta cx16.VERA_ADDR_L
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ply ; xbits
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lda p8v_maskbits,y
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}}
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if lores_mode {
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%asm {{
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stz cx16.VERA_CTRL
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stz cx16.VERA_ADDR_H
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lda p8v_xx+1
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lsr a
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lda p8v_xx
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ror a
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lsr a
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lsr a
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clc
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ldy p8v_yy
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adc p8v_times40_lsb,y
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sta cx16.VERA_ADDR_L
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lda p8v_times40_msb,y
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adc #0
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sta cx16.VERA_ADDR_M
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lda p8v_xx
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and #7
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tax
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lda p8v_maskbits,x
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}}
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} else {
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; width=640 (hires)
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%asm {{
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stz cx16.VERA_CTRL
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stz cx16.VERA_ADDR_H
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lda p8v_xx
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and #7
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pha ; xbits
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}}
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xx /= 8
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xx += yy*(640/8)
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%asm {{
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lda p8v_xx+1
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sta cx16.VERA_ADDR_M
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lda p8v_xx
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sta cx16.VERA_ADDR_L
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plx ; xbits
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lda p8v_maskbits,x
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}}
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}
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}
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}
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@ -718,10 +743,21 @@ invert:
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pha ; xbits
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}}
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xx /= 8
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if width==320
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xx += yy*(320/8) ; TODO *40 table
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if lores_mode {
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%asm {{
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; xx += yy * 40
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ldy p8v_yy
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lda p8v_xx
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clc
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adc p8v_times40_lsb,y
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sta p8v_xx
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lda p8v_xx+1
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adc p8v_times40_msb,y
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sta p8v_xx+1
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}}
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}
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else
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xx += yy*(640/8) ; TODO *80 table? (a bit large, need lo,mid,hi maybe just reuse *40 table and do 1 shift.)
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xx += yy*(640/8)
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%asm {{
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stz cx16.VERA_CTRL
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@ -830,10 +866,21 @@ skip:
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pha ; xbits
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}}
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xpos /= 8
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if width==320
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xpos += yy*(320/8) as uword ; TODO *40 table
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if lores_mode {
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%asm {{
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; xpos += yy*40
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ldy p8v_yy
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lda p8v_xpos
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clc
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adc p8v_times40_lsb,y
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sta p8v_xpos
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lda p8v_xpos+1
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adc p8v_times40_msb,y
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sta p8v_xpos+1
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}}
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}
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else
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xpos += yy*(640/8) as uword ; TODO *80 table? (a bit large, need lo,mid,hi maybe just reuse *40 table and do 1 shift.)
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xpos += yy*(640/8) as uword
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%asm {{
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stz cx16.VERA_CTRL
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@ -878,20 +925,63 @@ _doplot beq +
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}
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}
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sub position(uword @zp xx, uword yy) {
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if width==320
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cx16.r0 = yy*(320/8) ; TODO *40 table
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else
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cx16.r0 = yy*(640/8) ; TODO *80 table? (a bit large, need lo,mid,hi maybe just reuse *40 table and do 1 shift.)
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cx16.vaddr(0, cx16.r0+(xx/8), 0, 1)
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sub position(uword xx, uword yy) {
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if lores_mode {
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%asm {{
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stz cx16.VERA_CTRL
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lda p8v_xx+1
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lsr a
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lda p8v_xx
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ror a
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lsr a
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lsr a
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clc
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ldy p8v_yy
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adc p8v_times40_lsb,y
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sta cx16.VERA_ADDR_L
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lda p8v_times40_msb,y
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adc #0
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sta cx16.VERA_ADDR_M
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lda #%00010000 ; autoincr
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sta cx16.VERA_ADDR_H
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}}
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}
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else {
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cx16.r0 = yy*(640/8)
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cx16.vaddr(0, cx16.r0+(xx/8), 0, 1)
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}
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return
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}
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sub position2(uword @zp xx, uword yy, bool also_port_1) {
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sub position2(uword xx, uword yy) {
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position(xx, yy)
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if also_port_1
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cx16.vaddr_clone(0)
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; also set port 1 like that
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cx16.vaddr_clone(0)
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}
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; y*40 lookup table. Pretty compact because it all fits in a word and we only need 240 y positions.
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; a y*80 lookup table would be very large (lo,mid,hi for 480 values...)
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uword[240] @split @shared times40 = [
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0, 40, 80, 120, 160, 200, 240, 280, 320, 360, 400, 440, 480, 520, 560, 600,
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640, 680, 720, 760, 800, 840, 880, 920, 960, 1000, 1040, 1080, 1120, 1160,
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1200, 1240, 1280, 1320, 1360, 1400, 1440, 1480, 1520, 1560, 1600, 1640, 1680,
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1720, 1760, 1800, 1840, 1880, 1920, 1960, 2000, 2040, 2080, 2120, 2160, 2200,
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2240, 2280, 2320, 2360, 2400, 2440, 2480, 2520, 2560, 2600, 2640, 2680, 2720,
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2760, 2800, 2840, 2880, 2920, 2960, 3000, 3040, 3080, 3120, 3160, 3200, 3240,
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3280, 3320, 3360, 3400, 3440, 3480, 3520, 3560, 3600, 3640, 3680, 3720, 3760,
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3800, 3840, 3880, 3920, 3960, 4000, 4040, 4080, 4120, 4160, 4200, 4240, 4280,
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4320, 4360, 4400, 4440, 4480, 4520, 4560, 4600, 4640, 4680, 4720, 4760, 4800,
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4840, 4880, 4920, 4960, 5000, 5040, 5080, 5120, 5160, 5200, 5240, 5280, 5320,
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5360, 5400, 5440, 5480, 5520, 5560, 5600, 5640, 5680, 5720, 5760, 5800, 5840,
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5880, 5920, 5960, 6000, 6040, 6080, 6120, 6160, 6200, 6240, 6280, 6320, 6360,
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6400, 6440, 6480, 6520, 6560, 6600, 6640, 6680, 6720, 6760, 6800, 6840, 6880,
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6920, 6960, 7000, 7040, 7080, 7120, 7160, 7200, 7240, 7280, 7320, 7360, 7400,
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7440, 7480, 7520, 7560, 7600, 7640, 7680, 7720, 7760, 7800, 7840, 7880, 7920,
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7960, 8000, 8040, 8080, 8120, 8160, 8200, 8240, 8280, 8320, 8360, 8400, 8440,
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8480, 8520, 8560, 8600, 8640, 8680, 8720, 8760, 8800, 8840, 8880, 8920, 8960,
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9000, 9040, 9080, 9120, 9160, 9200, 9240, 9280, 9320, 9360, 9400, 9440, 9480,
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9520, 9560]
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const ubyte charset_bank = $1
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const uword charset_addr = $f000 ; in bank 1, so $1f000
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@ -948,7 +1038,7 @@ _doplot beq +
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bne --
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}}
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; left part of shifted char
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position2(xx, yy, true)
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position2(xx, yy)
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set_autoincrs()
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if draw {
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%asm {{
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@ -974,7 +1064,7 @@ cdraw_mod1 ora cx16.VERA_DATA1
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}
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; right part of shifted char
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if lsb(xx) & 7 !=0 {
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position2(xx+8, yy, true)
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position2(xx+8, yy)
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set_autoincrs()
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if draw {
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%asm {{
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@ -1005,7 +1095,7 @@ cdraw_mod2 ora cx16.VERA_DATA1
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sub set_autoincrs() {
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; set autoincrements to go to next pixel row (40 or 80 increment)
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if width==320 {
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if lores_mode {
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cx16.VERA_CTRL = 1
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cx16.VERA_ADDR_H = cx16.VERA_ADDR_H & $0f | (11<<4)
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cx16.VERA_CTRL = 0
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@ -1,6 +1,10 @@
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TODO
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====
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- optimize word addition word += mul40[indexbyte] to use adc with register indexed instructions
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- same with other operators (sbc, and, or, eor)
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- how is tye codegen for byte values here?
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- add paypal donation button as well?
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- announce prog8 on the 6502.org site?
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@ -74,7 +78,6 @@ IR/VM
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Libraries
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---------
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- Sorting module gnomesort_uw could be optimized more, rewrite in asm? Shellshort seems consistently faster even if most of the words are already sorted.
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- Monogfx: use *40 multiplication lookup tables (possibly *80 as well? but those are a bit large; needing lo,mid,hi)
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- Add split-word array sorting routines to sorting module?
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- pet32 target: make syslib more complete (missing kernal routines)?
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- need help with: PET disk routines (OPEN, SETLFS etc are not exposed as kernal calls)
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198
examples/test.p8
198
examples/test.p8
@ -1,9 +1,201 @@
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%zeropage basicsafe
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%import textio
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%import math
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%import monogfx
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%import gfx_lores
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%option no_sysinit
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main {
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sub start() {
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if not unexistingsymbol
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cx16.r0++
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math.rndseed(1234,8877)
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cbm.SETTIM(0,0,0)
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kernal()
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txt.print_uw(cbm.RDTIM16())
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sys.wait(200)
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math.rndseed(1234,8877)
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cbm.SETTIM(0,0,0)
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custom_256()
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txt.print_uw(cbm.RDTIM16())
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sys.wait(200)
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math.rndseed(1234,8877)
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cbm.SETTIM(0,0,0)
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custom_mono()
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txt.print_uw(cbm.RDTIM16())
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repeat {
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}
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}
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sub kernal() {
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cx16.set_screen_mode(128)
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cx16.GRAPH_set_colors(2,1,0)
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cx16.GRAPH_clear()
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repeat 1000 {
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cx16.r0 = math.rndw() % 320
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cx16.r1 = math.rnd() % 240
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cx16.r2 = math.rndw() % 320
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cx16.r3 = math.rnd() % 240
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cx16.GRAPH_draw_line(cx16.r0, cx16.r1, cx16.r2, cx16.r3)
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}
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cx16.set_screen_mode(0)
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}
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sub custom_mono() {
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monogfx.lores()
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repeat 1000 {
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cx16.r0 = math.rndw() % 320
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cx16.r1L = math.rnd() % 240
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cx16.r2 = math.rndw() % 320
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cx16.r3L = math.rnd() % 240
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line(cx16.r0, cx16.r1L, cx16.r2, cx16.r3L)
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}
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monogfx.textmode()
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}
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sub custom_256() {
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gfx_lores.graphics_mode()
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repeat 1000 {
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cx16.r0 = math.rndw() % 320
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cx16.r1L = math.rnd() % 240
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cx16.r2 = math.rndw() % 320
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cx16.r3L = math.rnd() % 240
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gfx_lores.line(cx16.r0, cx16.r1L, cx16.r2, cx16.r3L, 2)
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}
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gfx_lores.text_mode()
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}
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sub line(uword @zp x1, ubyte @zp y1, uword @zp x2, ubyte @zp y2) {
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; Bresenham algorithm.
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; This code special-cases various quadrant loops to allow simple ++ and -- operations.
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if y1>y2 {
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; make sure dy is always positive to have only 4 instead of 8 special cases
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cx16.r0 = x1
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x1 = x2
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x2 = cx16.r0
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cx16.r0L = y1
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y1 = y2
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y2 = cx16.r0L
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}
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word @zp dx = (x2 as word)-x1
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ubyte @zp dy = y2-y1
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if dx==0 {
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monogfx.vertical_line(x1, y1, abs(dy) as uword +1, true)
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return
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}
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if dy==0 {
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if x1>x2
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x1=x2
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monogfx.horizontal_line(x1, y1, abs(dx) as uword +1, true)
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return
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}
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cx16.r1L = 1 ;; true ; 'positive_ix'
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if dx < 0 {
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dx = -dx
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cx16.r1L = 0 ;; false
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}
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word @zp dx2 = dx*2
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word @zp dy2 = dy*2
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word @zp d = 0
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cx16.VERA_CTRL = 0
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cx16.VERA_ADDR_H = 0
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if dx >= dy {
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if cx16.r1L!=0 {
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repeat {
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plot()
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if x1==x2
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return
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x1++
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d += dy2
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if d > dx {
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y1++
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d -= dx2
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}
|
||||
}
|
||||
} else {
|
||||
repeat {
|
||||
plot()
|
||||
if x1==x2
|
||||
return
|
||||
x1--
|
||||
d += dy2
|
||||
if d > dx {
|
||||
y1++
|
||||
d -= dx2
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
if cx16.r1L!=0 {
|
||||
repeat {
|
||||
plot()
|
||||
if y1==y2
|
||||
return
|
||||
y1++
|
||||
d += dx2
|
||||
if d > dy {
|
||||
x1++
|
||||
d -= dy2
|
||||
}
|
||||
}
|
||||
} else {
|
||||
repeat {
|
||||
plot()
|
||||
if y1==y2
|
||||
return
|
||||
y1++
|
||||
d += dx2
|
||||
if d > dy {
|
||||
x1--
|
||||
d -= dy2
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
asmsub plot() {
|
||||
%asm {{
|
||||
lda p8v_x1+1
|
||||
lsr a
|
||||
lda p8v_x1
|
||||
ror a
|
||||
lsr a
|
||||
lsr a
|
||||
|
||||
clc
|
||||
ldy p8v_y1
|
||||
adc times40_lo,y
|
||||
sta cx16.VERA_ADDR_L
|
||||
lda times40_mid,y
|
||||
adc #0
|
||||
sta cx16.VERA_ADDR_M
|
||||
|
||||
lda p8v_x1
|
||||
and #7
|
||||
tax
|
||||
lda maskbits,x
|
||||
tsb cx16.VERA_DATA0
|
||||
rts
|
||||
|
||||
maskbits .byte 128,64,32,16,8,4,2,1
|
||||
; multiplication by 40 lookup table
|
||||
times40 := 40*range(240)
|
||||
|
||||
times40_lo .byte <times40
|
||||
times40_mid .byte >times40
|
||||
|
||||
; !notreached!
|
||||
}}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user