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https://github.com/irmen/prog8.git
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fixed lsb(value) not working when used in a comparison expression (needed to flip loading of A and Y register with the value)
This commit is contained in:
Irmen de Jong
parent
dd82e550d5
commit
6cb0e6a936
@ -1056,6 +1056,9 @@ internal class BuiltinFunctionsAsmGen(private val program: Program, private val
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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} else {
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} else {
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asmgen.assignExpressionToRegister(fcall.args.single(), RegisterOrPair.AY)
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asmgen.assignExpressionToRegister(fcall.args.single(), RegisterOrPair.AY)
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// NOTE: we rely on the fact that the above assignment to AY, assigns the Lsb to A as the last instruction.
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// this is required because the compiler assumes the status bits are set according to what A is (lsb)
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// and will not generate another cmp when lsb() is directly used inside a comparison expression.
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if (resultToStack)
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if (resultToStack)
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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asmgen.out(" sta P8ESTACK_LO,x | dex")
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}
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}
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@ -708,8 +708,8 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.A -> asmgen.out(" inx | lda P8ESTACK_LO,x")
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RegisterOrPair.A -> asmgen.out(" inx | lda P8ESTACK_LO,x")
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RegisterOrPair.X -> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
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RegisterOrPair.X -> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
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RegisterOrPair.Y -> asmgen.out(" inx | ldy P8ESTACK_LO,x")
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RegisterOrPair.Y -> asmgen.out(" inx | ldy P8ESTACK_LO,x")
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RegisterOrPair.AX -> asmgen.out(" inx | lda P8ESTACK_LO,x | ldx #0")
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RegisterOrPair.AX -> asmgen.out(" inx | txy | ldx #0 | lda P8ESTACK_LO,y")
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RegisterOrPair.AY -> asmgen.out(" inx | lda P8ESTACK_LO,x | ldy #0")
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RegisterOrPair.AY -> asmgen.out(" inx | ldy #0 | lda P8ESTACK_LO,x")
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in Cx16VirtualRegisters -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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asmgen.out("""
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inx
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inx
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@ -725,7 +725,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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DataType.UWORD, DataType.WORD, in PassByReferenceDatatypes -> {
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DataType.UWORD, DataType.WORD, in PassByReferenceDatatypes -> {
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when(target.register!!) {
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when(target.register!!) {
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RegisterOrPair.AX -> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
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RegisterOrPair.AX -> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
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RegisterOrPair.AY-> asmgen.out(" inx | lda P8ESTACK_LO,x | ldy P8ESTACK_HI,x")
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RegisterOrPair.AY-> asmgen.out(" inx | ldy P8ESTACK_HI,x | lda P8ESTACK_LO,x")
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RegisterOrPair.XY-> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
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RegisterOrPair.XY-> throw AssemblyError("can't load X from stack here - use intermediary var? ${target.origAstTarget?.position}")
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in Cx16VirtualRegisters -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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asmgen.out("""
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@ -773,9 +773,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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TargetStorageKind.REGISTER -> {
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TargetStorageKind.REGISTER -> {
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when(target.register!!) {
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when(target.register!!) {
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RegisterOrPair.AX -> asmgen.out(" lda #<$sourceName | ldx #>$sourceName")
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RegisterOrPair.AX -> asmgen.out(" ldx #>$sourceName | lda #<$sourceName")
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RegisterOrPair.AY -> asmgen.out(" lda #<$sourceName | ldy #>$sourceName")
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RegisterOrPair.AY -> asmgen.out(" ldy #>$sourceName | lda #<$sourceName")
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RegisterOrPair.XY -> asmgen.out(" ldx #<$sourceName | ldy #>$sourceName")
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RegisterOrPair.XY -> asmgen.out(" ldy #>$sourceName | ldx #<$sourceName")
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in Cx16VirtualRegisters -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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asmgen.out("""
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lda #<$sourceName
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lda #<$sourceName
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@ -914,9 +914,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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TargetStorageKind.REGISTER -> {
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TargetStorageKind.REGISTER -> {
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when(target.register!!) {
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when(target.register!!) {
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RegisterOrPair.AX -> asmgen.out(" lda $sourceName | ldx $sourceName+1")
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RegisterOrPair.AX -> asmgen.out(" ldx $sourceName+1 | lda $sourceName")
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RegisterOrPair.AY -> asmgen.out(" lda $sourceName | ldy $sourceName+1")
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RegisterOrPair.AY -> asmgen.out(" ldy $sourceName+1 | lda $sourceName")
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RegisterOrPair.XY -> asmgen.out(" ldx $sourceName | ldy $sourceName+1")
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RegisterOrPair.XY -> asmgen.out(" ldy $sourceName+1 | ldx $sourceName")
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in Cx16VirtualRegisters -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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asmgen.out("""
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lda $sourceName
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lda $sourceName
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@ -1086,9 +1086,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.A -> asmgen.out(" lda $sourceName")
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RegisterOrPair.A -> asmgen.out(" lda $sourceName")
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RegisterOrPair.X -> asmgen.out(" ldx $sourceName")
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RegisterOrPair.X -> asmgen.out(" ldx $sourceName")
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RegisterOrPair.Y -> asmgen.out(" ldy $sourceName")
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RegisterOrPair.Y -> asmgen.out(" ldy $sourceName")
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RegisterOrPair.AX -> asmgen.out(" lda $sourceName | ldx #0")
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RegisterOrPair.AX -> asmgen.out(" ldx #0 | lda $sourceName")
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RegisterOrPair.AY -> asmgen.out(" lda $sourceName | ldy #0")
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RegisterOrPair.AY -> asmgen.out(" ldy #0 | lda $sourceName")
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RegisterOrPair.XY -> asmgen.out(" ldx $sourceName | ldy #0")
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RegisterOrPair.XY -> asmgen.out(" ldy #0 | ldx $sourceName")
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
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in Cx16VirtualRegisters -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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asmgen.out("""
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@ -1203,9 +1203,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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TargetStorageKind.REGISTER -> {
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TargetStorageKind.REGISTER -> {
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when(wordtarget.register!!) {
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when(wordtarget.register!!) {
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RegisterOrPair.AX -> asmgen.out(" lda $sourceName | ldx #0")
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RegisterOrPair.AX -> asmgen.out(" ldx #0 | lda $sourceName")
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RegisterOrPair.AY -> asmgen.out(" lda $sourceName | ldy #0")
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RegisterOrPair.AY -> asmgen.out(" ldy #0 | lda $sourceName")
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RegisterOrPair.XY -> asmgen.out(" ldx $sourceName | ldy #0")
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RegisterOrPair.XY -> asmgen.out(" ldy #0 | ldx $sourceName")
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else -> throw AssemblyError("only reg pairs are words")
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else -> throw AssemblyError("only reg pairs are words")
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}
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}
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}
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}
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@ -1466,9 +1466,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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TargetStorageKind.REGISTER -> {
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TargetStorageKind.REGISTER -> {
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when(target.register!!) {
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when(target.register!!) {
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RegisterOrPair.AX -> asmgen.out(" lda #<${word.toHex()} | ldx #>${word.toHex()}")
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RegisterOrPair.AX -> asmgen.out(" ldx #>${word.toHex()} | lda #<${word.toHex()}")
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RegisterOrPair.AY -> asmgen.out(" lda #<${word.toHex()} | ldy #>${word.toHex()}")
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RegisterOrPair.AY -> asmgen.out(" ldy #>${word.toHex()} | lda #<${word.toHex()}")
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RegisterOrPair.XY -> asmgen.out(" ldx #<${word.toHex()} | ldy #>${word.toHex()}")
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RegisterOrPair.XY -> asmgen.out(" ldy #>${word.toHex()} | ldx #<${word.toHex()}")
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in Cx16VirtualRegisters -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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asmgen.out("""
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lda #<${word.toHex()}
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lda #<${word.toHex()}
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@ -1554,9 +1554,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.A -> asmgen.out(" lda #${byte.toHex()}")
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RegisterOrPair.A -> asmgen.out(" lda #${byte.toHex()}")
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RegisterOrPair.X -> asmgen.out(" ldx #${byte.toHex()}")
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RegisterOrPair.X -> asmgen.out(" ldx #${byte.toHex()}")
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RegisterOrPair.Y -> asmgen.out(" ldy #${byte.toHex()}")
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RegisterOrPair.Y -> asmgen.out(" ldy #${byte.toHex()}")
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RegisterOrPair.AX -> asmgen.out(" lda #${byte.toHex()} | ldx #0")
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RegisterOrPair.AX -> asmgen.out(" ldx #0 | lda #${byte.toHex()}")
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RegisterOrPair.AY -> asmgen.out(" lda #${byte.toHex()} | ldy #0")
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RegisterOrPair.AY -> asmgen.out(" ldy #0 | lda #${byte.toHex()}")
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RegisterOrPair.XY -> asmgen.out(" ldx #${byte.toHex()} | ldy #0")
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RegisterOrPair.XY -> asmgen.out(" ldy #0 | ldx #${byte.toHex()}")
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
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in Cx16VirtualRegisters -> {
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in Cx16VirtualRegisters -> {
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asmgen.out(" lda #${byte.toHex()} | sta cx16.${target.register.toString().toLowerCase()}")
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asmgen.out(" lda #${byte.toHex()} | sta cx16.${target.register.toString().toLowerCase()}")
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@ -1731,9 +1731,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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RegisterOrPair.A -> asmgen.out(" lda ${address.toHex()}")
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RegisterOrPair.A -> asmgen.out(" lda ${address.toHex()}")
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RegisterOrPair.X -> asmgen.out(" ldx ${address.toHex()}")
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RegisterOrPair.X -> asmgen.out(" ldx ${address.toHex()}")
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RegisterOrPair.Y -> asmgen.out(" ldy ${address.toHex()}")
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RegisterOrPair.Y -> asmgen.out(" ldy ${address.toHex()}")
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RegisterOrPair.AX -> asmgen.out(" lda ${address.toHex()} | ldx #0")
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RegisterOrPair.AX -> asmgen.out(" ldx #0 | lda ${address.toHex()}")
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RegisterOrPair.AY -> asmgen.out(" lda ${address.toHex()} | ldy #0")
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RegisterOrPair.AY -> asmgen.out(" ldy #0 | lda ${address.toHex()}")
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RegisterOrPair.XY -> asmgen.out(" ldy ${address.toHex()} | ldy #0")
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RegisterOrPair.XY -> asmgen.out(" ldy #0 | ldy ${address.toHex()}")
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
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RegisterOrPair.FAC1, RegisterOrPair.FAC2 -> throw AssemblyError("expected typecasted byte to float")
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in Cx16VirtualRegisters -> {
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in Cx16VirtualRegisters -> {
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asmgen.out("""
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asmgen.out("""
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@ -1807,9 +1807,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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throw AssemblyError("no asm gen for assign memory byte at $address to array ${wordtarget.asmVarname}")
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throw AssemblyError("no asm gen for assign memory byte at $address to array ${wordtarget.asmVarname}")
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}
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}
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TargetStorageKind.REGISTER -> when(wordtarget.register!!) {
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TargetStorageKind.REGISTER -> when(wordtarget.register!!) {
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RegisterOrPair.AX -> asmgen.out(" lda ${address.toHex()} | ldx #0")
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RegisterOrPair.AX -> asmgen.out(" ldx #0 | lda ${address.toHex()}")
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RegisterOrPair.AY -> asmgen.out(" lda ${address.toHex()} | ldy #0")
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RegisterOrPair.AY -> asmgen.out(" ldy #0 | lda ${address.toHex()}")
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RegisterOrPair.XY -> asmgen.out(" ldy ${address.toHex()} | ldy #0")
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RegisterOrPair.XY -> asmgen.out(" ldy #0 | ldy ${address.toHex()}")
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else -> throw AssemblyError("word regs can only be pair")
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else -> throw AssemblyError("word regs can only be pair")
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}
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}
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TargetStorageKind.STACK -> {
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TargetStorageKind.STACK -> {
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@ -8,17 +8,46 @@ main {
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sub start () {
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sub start () {
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uword length
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uword length
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uword total = 0
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if length>256 {
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length=200
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repeat length-1
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count()
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gfx2.next_pixel(color)
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txt.print_uw(total)
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} else {
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txt.chrout('\n')
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repeat (length-1) as ubyte ; TODO lsb(length-1) doesn't work!?!?!?
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length=255
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gfx2.next_pixel(color)
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count()
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}
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txt.print_uw(total)
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txt.chrout('\n')
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length=256
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count()
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txt.print_uw(total)
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txt.chrout('\n')
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length=257
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count()
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txt.print_uw(total)
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txt.chrout('\n')
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length=9999
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count()
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txt.print_uw(total)
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txt.chrout('\n')
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test_stack.test()
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test_stack.test()
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sub count() {
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total = 0
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if length>256 {
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repeat length-1
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total++
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} else {
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uword total2
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repeat lsb(length-1)
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total++
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; repeat (length-1) as ubyte ; TODO lsb(length-1) doesn't work!?!?!?
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; total++
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}
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}
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}
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}
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}
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}
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