From 6ddb7453e1ac60ffb32522a5eb0c62d8aaa265ca Mon Sep 17 00:00:00 2001 From: Irmen de Jong Date: Thu, 31 Mar 2022 02:02:38 +0200 Subject: [PATCH] vm postincrdecr on array done --- .../src/prog8/codegen/virtual/CodeGen.kt | 22 ++++++- .../prog8/codegen/virtual/ExpressionGen.kt | 3 +- docs/source/todo.rst | 3 +- examples/test.p8 | 61 ++++++------------- 4 files changed, 42 insertions(+), 47 deletions(-) diff --git a/codeGenVirtual/src/prog8/codegen/virtual/CodeGen.kt b/codeGenVirtual/src/prog8/codegen/virtual/CodeGen.kt index e9e3d53f3..8136373e4 100644 --- a/codeGenVirtual/src/prog8/codegen/virtual/CodeGen.kt +++ b/codeGenVirtual/src/prog8/codegen/virtual/CodeGen.kt @@ -386,7 +386,25 @@ class CodeGen(internal val program: PtProgram, code += VmCodeInstruction(operation, vmDt, reg1=resultReg) code += VmCodeInstruction(Opcode.STOREI, vmDt, reg1=resultReg, reg2=addressReg) } else if (array!=null) { - TODO("postincrdecr array") + val variable = array.variable.targetName + var variableAddr = allocations.get(variable) + val itemsize = program.memsizer.memorySize(array.type) + val fixedIndex = (array.index as? PtNumber)?.number?.toInt() + val memOp = when(postIncrDecr.operator) { + "++" -> Opcode.INCM + "--" -> Opcode.DECM + else -> throw AssemblyError("weird operator") + } + if(fixedIndex!=null) { + variableAddr += fixedIndex*itemsize + code += VmCodeInstruction(memOp, vmDt, value=variableAddr) + } else { + val indexReg = vmRegisters.nextFree() + code += expressionEval.translateExpression(array.index, indexReg) + code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=resultReg, reg2=indexReg, value=variableAddr) + code += VmCodeInstruction(operation, vmDt, reg1=resultReg) + code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1=resultReg, reg2=indexReg, value=variableAddr) + } } else throw AssemblyError("weird assigntarget") @@ -526,7 +544,7 @@ class CodeGen(internal val program: PtProgram, private var labelSequenceNumber = 0 internal fun createLabelName(): List { labelSequenceNumber++ - return listOf("generated$labelSequenceNumber") + return listOf("prog8_label_gen_$labelSequenceNumber") } internal fun translateBuiltinFunc(call: PtBuiltinFunctionCall, resultRegister: Int): VmCodeChunk = diff --git a/codeGenVirtual/src/prog8/codegen/virtual/ExpressionGen.kt b/codeGenVirtual/src/prog8/codegen/virtual/ExpressionGen.kt index 5610fcb26..64f696b5d 100644 --- a/codeGenVirtual/src/prog8/codegen/virtual/ExpressionGen.kt +++ b/codeGenVirtual/src/prog8/codegen/virtual/ExpressionGen.kt @@ -96,11 +96,12 @@ internal class ExpressionGen(private val codeGen: CodeGen) { val vmDt = codeGen.vmType(arrayIx.type) val code = VmCodeChunk() val idxReg = codeGen.vmRegisters.nextFree() + // TODO: optimized code when the index is a constant value code += translateExpression(arrayIx.index, idxReg) if(eltSize>1) { val factorReg = codeGen.vmRegisters.nextFree() code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=factorReg, value=eltSize) - code += VmCodeInstruction(Opcode.MUL, VmDataType.BYTE, reg1=idxReg, reg2=factorReg) + code += VmCodeInstruction(Opcode.MUL, VmDataType.BYTE, reg1=idxReg, reg2=idxReg, reg3=factorReg) } val arrayLocation = codeGen.allocations.get(arrayIx.variable.targetName) code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=idxReg, value = arrayLocation) diff --git a/docs/source/todo.rst b/docs/source/todo.rst index 33e52b71b..89381939c 100644 --- a/docs/source/todo.rst +++ b/docs/source/todo.rst @@ -16,11 +16,12 @@ For next release can we make the code read the new layout from vera registers instead of hardcoding it? - x16: optimize diskio load_raw because headerless files are now supported https://github.com/commanderx16/x16-rom/pull/216 note: must still work on c64/c128 that don't have this! +- x16: cleanup references to r38/r39 in the docs and code +- x16: fix the separate applications as well (assembler, ...) - vm codegen: When - vm codegen: Pipe expression - vm codegen: validate that PtFunctionCall translation works okay with resultregister, and multiple paramsters in correct order -- vm codegen: postincrdecr arrayvalue - vm: support no globals re-init option - vm: how to remove all unused subroutines? (for asm, 64tass used to do this) - vm: rather than being able to jump to any 'address' (IPTR), use 'blocks' diff --git a/examples/test.p8 b/examples/test.p8 index fa576d9cf..fef625c3f 100644 --- a/examples/test.p8 +++ b/examples/test.p8 @@ -6,56 +6,31 @@ main { sub start() { txt.clear_screen() txt.print("Welcome to a prog8 pixel shader :-)\n") - uword ww = 0 - ubyte bc - uword wc - for bc in "irmen" { - txt.chrout(bc) - ww++ - } - txt.print_uw(ww) ; 5 + byte[] barr = [-1,-2,-3] + uword[] uwarr = [1111,2222,3333] + + txt.print_b(barr[2]) + txt.spc() + txt.print_uw(uwarr[2]) txt.nl() - for bc in [10,11,12] { - txt.print_ub(bc) - txt.spc() - ww++ - } - txt.print_uw(ww) ; 8 - txt.nl() + barr[2] -- + uwarr[2] -- + + txt.print_b(barr[2]) + txt.spc() + txt.print_uw(uwarr[2]) txt.nl() - for wc in [4097,8193,16385] { - txt.print_uw(wc) - txt.spc() - ww++ - } - txt.print_uw(ww) ; 11 + barr[2] ++ + uwarr[2] ++ + + txt.print_b(barr[2]) + txt.spc() + txt.print_uw(uwarr[2]) txt.nl() - ubyte rfrom = 10 - ubyte rto = 17 - - for bc in rfrom to rto step 2 { - ; 10,12,14,16 - txt.print_ub(bc) - txt.spc() - ww++ - } - txt.print_uw(ww) ; 15 - txt.nl() - - for bc in 30 to 0 step -4 { - ; 30,26,22,18,14,10,6,2 - txt.print_ub(bc) - txt.spc() - ww++ - } - txt.print_uw(ww) ; 23 - txt.nl() - - sys.exit(99)