mirror of
https://github.com/irmen/prog8.git
synced 2024-11-29 17:50:35 +00:00
vm postincrdecr on array done
This commit is contained in:
parent
ad2355f8d3
commit
6ddb7453e1
@ -386,7 +386,25 @@ class CodeGen(internal val program: PtProgram,
|
|||||||
code += VmCodeInstruction(operation, vmDt, reg1=resultReg)
|
code += VmCodeInstruction(operation, vmDt, reg1=resultReg)
|
||||||
code += VmCodeInstruction(Opcode.STOREI, vmDt, reg1=resultReg, reg2=addressReg)
|
code += VmCodeInstruction(Opcode.STOREI, vmDt, reg1=resultReg, reg2=addressReg)
|
||||||
} else if (array!=null) {
|
} else if (array!=null) {
|
||||||
TODO("postincrdecr array")
|
val variable = array.variable.targetName
|
||||||
|
var variableAddr = allocations.get(variable)
|
||||||
|
val itemsize = program.memsizer.memorySize(array.type)
|
||||||
|
val fixedIndex = (array.index as? PtNumber)?.number?.toInt()
|
||||||
|
val memOp = when(postIncrDecr.operator) {
|
||||||
|
"++" -> Opcode.INCM
|
||||||
|
"--" -> Opcode.DECM
|
||||||
|
else -> throw AssemblyError("weird operator")
|
||||||
|
}
|
||||||
|
if(fixedIndex!=null) {
|
||||||
|
variableAddr += fixedIndex*itemsize
|
||||||
|
code += VmCodeInstruction(memOp, vmDt, value=variableAddr)
|
||||||
|
} else {
|
||||||
|
val indexReg = vmRegisters.nextFree()
|
||||||
|
code += expressionEval.translateExpression(array.index, indexReg)
|
||||||
|
code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=resultReg, reg2=indexReg, value=variableAddr)
|
||||||
|
code += VmCodeInstruction(operation, vmDt, reg1=resultReg)
|
||||||
|
code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1=resultReg, reg2=indexReg, value=variableAddr)
|
||||||
|
}
|
||||||
} else
|
} else
|
||||||
throw AssemblyError("weird assigntarget")
|
throw AssemblyError("weird assigntarget")
|
||||||
|
|
||||||
@ -526,7 +544,7 @@ class CodeGen(internal val program: PtProgram,
|
|||||||
private var labelSequenceNumber = 0
|
private var labelSequenceNumber = 0
|
||||||
internal fun createLabelName(): List<String> {
|
internal fun createLabelName(): List<String> {
|
||||||
labelSequenceNumber++
|
labelSequenceNumber++
|
||||||
return listOf("generated$labelSequenceNumber")
|
return listOf("prog8_label_gen_$labelSequenceNumber")
|
||||||
}
|
}
|
||||||
|
|
||||||
internal fun translateBuiltinFunc(call: PtBuiltinFunctionCall, resultRegister: Int): VmCodeChunk =
|
internal fun translateBuiltinFunc(call: PtBuiltinFunctionCall, resultRegister: Int): VmCodeChunk =
|
||||||
|
@ -96,11 +96,12 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
|
|||||||
val vmDt = codeGen.vmType(arrayIx.type)
|
val vmDt = codeGen.vmType(arrayIx.type)
|
||||||
val code = VmCodeChunk()
|
val code = VmCodeChunk()
|
||||||
val idxReg = codeGen.vmRegisters.nextFree()
|
val idxReg = codeGen.vmRegisters.nextFree()
|
||||||
|
// TODO: optimized code when the index is a constant value
|
||||||
code += translateExpression(arrayIx.index, idxReg)
|
code += translateExpression(arrayIx.index, idxReg)
|
||||||
if(eltSize>1) {
|
if(eltSize>1) {
|
||||||
val factorReg = codeGen.vmRegisters.nextFree()
|
val factorReg = codeGen.vmRegisters.nextFree()
|
||||||
code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=factorReg, value=eltSize)
|
code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=factorReg, value=eltSize)
|
||||||
code += VmCodeInstruction(Opcode.MUL, VmDataType.BYTE, reg1=idxReg, reg2=factorReg)
|
code += VmCodeInstruction(Opcode.MUL, VmDataType.BYTE, reg1=idxReg, reg2=idxReg, reg3=factorReg)
|
||||||
}
|
}
|
||||||
val arrayLocation = codeGen.allocations.get(arrayIx.variable.targetName)
|
val arrayLocation = codeGen.allocations.get(arrayIx.variable.targetName)
|
||||||
code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=idxReg, value = arrayLocation)
|
code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=resultRegister, reg2=idxReg, value = arrayLocation)
|
||||||
|
@ -16,11 +16,12 @@ For next release
|
|||||||
can we make the code read the new layout from vera registers instead of hardcoding it?
|
can we make the code read the new layout from vera registers instead of hardcoding it?
|
||||||
- x16: optimize diskio load_raw because headerless files are now supported https://github.com/commanderx16/x16-rom/pull/216
|
- x16: optimize diskio load_raw because headerless files are now supported https://github.com/commanderx16/x16-rom/pull/216
|
||||||
note: must still work on c64/c128 that don't have this!
|
note: must still work on c64/c128 that don't have this!
|
||||||
|
- x16: cleanup references to r38/r39 in the docs and code
|
||||||
|
- x16: fix the separate applications as well (assembler, ...)
|
||||||
|
|
||||||
- vm codegen: When
|
- vm codegen: When
|
||||||
- vm codegen: Pipe expression
|
- vm codegen: Pipe expression
|
||||||
- vm codegen: validate that PtFunctionCall translation works okay with resultregister, and multiple paramsters in correct order
|
- vm codegen: validate that PtFunctionCall translation works okay with resultregister, and multiple paramsters in correct order
|
||||||
- vm codegen: postincrdecr arrayvalue
|
|
||||||
- vm: support no globals re-init option
|
- vm: support no globals re-init option
|
||||||
- vm: how to remove all unused subroutines? (for asm, 64tass used to do this)
|
- vm: how to remove all unused subroutines? (for asm, 64tass used to do this)
|
||||||
- vm: rather than being able to jump to any 'address' (IPTR), use 'blocks'
|
- vm: rather than being able to jump to any 'address' (IPTR), use 'blocks'
|
||||||
|
@ -6,56 +6,31 @@ main {
|
|||||||
sub start() {
|
sub start() {
|
||||||
txt.clear_screen()
|
txt.clear_screen()
|
||||||
txt.print("Welcome to a prog8 pixel shader :-)\n")
|
txt.print("Welcome to a prog8 pixel shader :-)\n")
|
||||||
uword ww = 0
|
|
||||||
ubyte bc
|
|
||||||
uword wc
|
|
||||||
|
|
||||||
for bc in "irmen" {
|
byte[] barr = [-1,-2,-3]
|
||||||
txt.chrout(bc)
|
uword[] uwarr = [1111,2222,3333]
|
||||||
ww++
|
|
||||||
}
|
txt.print_b(barr[2])
|
||||||
txt.print_uw(ww) ; 5
|
txt.spc()
|
||||||
|
txt.print_uw(uwarr[2])
|
||||||
txt.nl()
|
txt.nl()
|
||||||
|
|
||||||
for bc in [10,11,12] {
|
barr[2] --
|
||||||
txt.print_ub(bc)
|
uwarr[2] --
|
||||||
txt.spc()
|
|
||||||
ww++
|
txt.print_b(barr[2])
|
||||||
}
|
txt.spc()
|
||||||
txt.print_uw(ww) ; 8
|
txt.print_uw(uwarr[2])
|
||||||
txt.nl()
|
|
||||||
txt.nl()
|
txt.nl()
|
||||||
|
|
||||||
for wc in [4097,8193,16385] {
|
barr[2] ++
|
||||||
txt.print_uw(wc)
|
uwarr[2] ++
|
||||||
txt.spc()
|
|
||||||
ww++
|
txt.print_b(barr[2])
|
||||||
}
|
txt.spc()
|
||||||
txt.print_uw(ww) ; 11
|
txt.print_uw(uwarr[2])
|
||||||
txt.nl()
|
txt.nl()
|
||||||
|
|
||||||
ubyte rfrom = 10
|
|
||||||
ubyte rto = 17
|
|
||||||
|
|
||||||
for bc in rfrom to rto step 2 {
|
|
||||||
; 10,12,14,16
|
|
||||||
txt.print_ub(bc)
|
|
||||||
txt.spc()
|
|
||||||
ww++
|
|
||||||
}
|
|
||||||
txt.print_uw(ww) ; 15
|
|
||||||
txt.nl()
|
|
||||||
|
|
||||||
for bc in 30 to 0 step -4 {
|
|
||||||
; 30,26,22,18,14,10,6,2
|
|
||||||
txt.print_ub(bc)
|
|
||||||
txt.spc()
|
|
||||||
ww++
|
|
||||||
}
|
|
||||||
txt.print_uw(ww) ; 23
|
|
||||||
txt.nl()
|
|
||||||
|
|
||||||
|
|
||||||
sys.exit(99)
|
sys.exit(99)
|
||||||
|
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user