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https://github.com/irmen/prog8.git
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refactoring assignments codegen
This commit is contained in:
Irmen de Jong
parent
c144d4e501
commit
6f3b2749b0
@ -328,7 +328,7 @@ open class Assignment(var target: AssignTarget, var value: Expression, override
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return("Assignment(target: $target, value: $value, pos=$position)")
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}
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val isInplace: Boolean
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val isAugmentable: Boolean
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get() {
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val binExpr = value as? BinaryExpression
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if(binExpr!=null) {
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@ -1025,36 +1025,6 @@ $counterVar .byte 0""")
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internal fun translateFunctionCall(functionCall: FunctionCall) =
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functioncallAsmGen.translateFunctionCall(functionCall)
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internal fun assignFromEvalResult(target: AssignTarget) =
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assignmentAsmGen.assignFromEvalResult(target)
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fun assignFromByteConstant(target: AssignTarget, value: Short) =
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assignmentAsmGen.assignFromByteConstant(target, value)
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fun assignFromWordConstant(target: AssignTarget, value: Int) =
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assignmentAsmGen.assignFromWordConstant(target, value)
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fun assignFromFloatConstant(target: AssignTarget, value: Double) =
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assignmentAsmGen.assignFromFloatConstant(target, value)
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fun assignFromByteVariable(target: AssignTarget, variable: IdentifierReference) =
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assignmentAsmGen.assignFromByteVariable(target, variable)
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fun assignFromWordVariable(target: AssignTarget, variable: IdentifierReference) =
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assignmentAsmGen.assignFromWordVariable(target, variable)
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fun assignFromAddressOf(target: AssignTarget, variable: IdentifierReference) =
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assignmentAsmGen.assignFromAddressOf(target, variable)
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fun assignFromFloatVariable(target: AssignTarget, variable: IdentifierReference) =
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assignmentAsmGen.assignFromFloatVariable(target, variable)
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fun assignFromRegister(target: AssignTarget, register: CpuRegister) =
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assignmentAsmGen.assignFromRegister(target, register)
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fun assignFromMemoryByte(target: AssignTarget, address: Int?, identifier: IdentifierReference?) =
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assignmentAsmGen.assignFromMemoryByte(target, address, identifier)
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fun assignToRegister(reg: CpuRegister, value: Short?, identifier: IdentifierReference?) =
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internal fun assignToRegister(reg: CpuRegister, value: Short?, identifier: IdentifierReference?) =
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assignmentAsmGen.assignToRegister(reg, value, identifier)
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}
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@ -3,10 +3,7 @@ package prog8.compiler.target.c64.codegen
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import prog8.ast.Program
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import prog8.ast.base.*
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import prog8.ast.expressions.*
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import prog8.ast.statements.AssignTarget
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import prog8.ast.statements.Assignment
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import prog8.ast.statements.DirectMemoryWrite
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import prog8.ast.statements.VarDecl
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import prog8.ast.statements.*
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import prog8.compiler.AssemblyError
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import prog8.compiler.target.c64.C64MachineDefinition
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import prog8.compiler.target.c64.C64MachineDefinition.C64Zeropage
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@ -18,33 +15,49 @@ import prog8.compiler.toHex
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internal class AssignmentAsmGen(private val program: Program, private val asmgen: AsmGen) {
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internal fun translate(assign: Assignment) {
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if(assign.isInplace)
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translateNormalAssignment(assign) // TODO generate better code here for in-place assignments
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else
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translateNormalAssignment(assign)
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when {
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assign.value is NumericLiteralValue -> translateConstantValueAssignment(assign)
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assign.value is IdentifierReference -> translateVariableAssignment(assign)
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assign.isAugmentable -> {
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println("TODO: optimize augmentable assignment ${assign.position}") // TODO
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translateOtherAssignment(assign) // TODO generate better code here for augmentable assignments
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}
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else -> translateOtherAssignment(assign)
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}
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}
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// old code-generation below:
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// eventually, all of this should have been replaced by newer more optimized code.
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private fun translateNormalAssignment(assign: Assignment) {
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internal fun assignToRegister(reg: CpuRegister, value: Short?, identifier: IdentifierReference?) {
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if(value!=null) {
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asmgen.out(" ld${reg.toString().toLowerCase()} #${value.toHex()}")
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} else if(identifier!=null) {
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val name = asmgen.asmIdentifierName(identifier)
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asmgen.out(" ld${reg.toString().toLowerCase()} $name")
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}
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}
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private fun translateVariableAssignment(assign: Assignment) {
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val identifier = assign.value as IdentifierReference
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when (val type = assign.target.inferType(program, assign).typeOrElse(DataType.STRUCT)) {
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DataType.UBYTE, DataType.BYTE -> assignFromByteVariable(assign.target, identifier)
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DataType.UWORD, DataType.WORD -> assignFromWordVariable(assign.target, identifier)
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DataType.FLOAT -> assignFromFloatVariable(assign.target, identifier)
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in PassByReferenceDatatypes -> assignFromAddressOf(assign.target, identifier)
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else -> throw AssemblyError("unsupported assignment target type $type")
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}
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}
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private fun translateConstantValueAssignment(assign: Assignment) {
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val numVal = assign.value as NumericLiteralValue
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when (numVal.type) {
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DataType.UBYTE, DataType.BYTE -> assignFromByteConstant(assign.target, numVal.number.toShort())
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DataType.UWORD, DataType.WORD -> assignFromWordConstant(assign.target, numVal.number.toInt())
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DataType.FLOAT -> assignFromFloatConstant(assign.target, numVal.number.toDouble())
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else -> throw AssemblyError("weird numval type")
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}
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}
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private fun translateOtherAssignment(assign: Assignment) {
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when (assign.value) {
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is NumericLiteralValue -> {
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val numVal = assign.value as NumericLiteralValue
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when (numVal.type) {
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DataType.UBYTE, DataType.BYTE -> assignFromByteConstant(assign.target, numVal.number.toShort())
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DataType.UWORD, DataType.WORD -> assignFromWordConstant(assign.target, numVal.number.toInt())
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DataType.FLOAT -> assignFromFloatConstant(assign.target, numVal.number.toDouble())
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else -> throw AssemblyError("weird numval type")
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}
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}
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is IdentifierReference -> {
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when (val type = assign.target.inferType(program, assign).typeOrElse(DataType.STRUCT)) {
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DataType.UBYTE, DataType.BYTE -> assignFromByteVariable(assign.target, assign.value as IdentifierReference)
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DataType.UWORD, DataType.WORD -> assignFromWordVariable(assign.target, assign.value as IdentifierReference)
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DataType.FLOAT -> assignFromFloatVariable(assign.target, assign.value as IdentifierReference)
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else -> throw AssemblyError("unsupported assignment target type $type")
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}
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}
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is AddressOf -> {
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val identifier = (assign.value as AddressOf).identifier
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assignFromAddressOf(assign.target, identifier)
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@ -60,7 +73,9 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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assignFromMemoryByte(assign.target, null, read.addressExpression as IdentifierReference)
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}
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else -> {
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throw AssemblyError("missing asm gen for memread assignment into ${assign.target}")
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asmgen.translateExpression(read.addressExpression)
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asmgen.out(" jsr prog8_lib.read_byte_from_address | inx")
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assignFromRegister(assign.target, CpuRegister.A)
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}
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}
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}
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@ -120,10 +135,11 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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is ArrayLiteralValue, is StringLiteralValue -> throw AssemblyError("no asm gen for string/array assignment $assign")
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is RangeExpr -> throw AssemblyError("range expression should have been changed into array values ${assign.value.position}")
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else -> throw AssemblyError("assignment value type should have been handled elsewhere")
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}
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}
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internal fun assignFromEvalResult(target: AssignTarget) {
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private fun assignFromEvalResult(target: AssignTarget) {
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val targetIdent = target.identifier
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when {
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targetIdent != null -> {
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@ -152,8 +168,8 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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target.memoryAddress != null -> {
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asmgen.out(" inx | ldy $ESTACK_LO_HEX,x")
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storeRegisterInMemoryAddress(CpuRegister.Y, target.memoryAddress)
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asmgen.out(" inx")
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storeByteViaRegisterAInMemoryAddress("$ESTACK_LO_HEX,x", target.memoryAddress)
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}
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target.arrayindexed != null -> {
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val arrayDt = target.arrayindexed!!.identifier.inferType(program).typeOrElse(DataType.STRUCT)
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@ -166,7 +182,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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internal fun assignFromAddressOf(target: AssignTarget, name: IdentifierReference) {
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private fun assignFromAddressOf(target: AssignTarget, name: IdentifierReference) {
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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val struct = name.memberOfStruct(program.namespace)
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@ -204,7 +220,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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internal fun assignFromWordVariable(target: AssignTarget, variable: IdentifierReference) {
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private fun assignFromWordVariable(target: AssignTarget, variable: IdentifierReference) {
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val sourceName = asmgen.asmIdentifierName(variable)
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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@ -234,7 +250,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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internal fun assignFromFloatVariable(target: AssignTarget, variable: IdentifierReference) {
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private fun assignFromFloatVariable(target: AssignTarget, variable: IdentifierReference) {
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val sourceName = asmgen.asmIdentifierName(variable)
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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@ -265,7 +281,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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internal fun assignFromByteVariable(target: AssignTarget, variable: IdentifierReference) {
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private fun assignFromByteVariable(target: AssignTarget, variable: IdentifierReference) {
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val sourceName = asmgen.asmIdentifierName(variable)
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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@ -296,16 +312,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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asmgen.out(" lda $sourceName | sta $targetName")
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}
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else -> {
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asmgen.translateExpression(addressExpr)
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asmgen.out("""
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inx
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lda $ESTACK_LO_HEX,x
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ldy $ESTACK_HI_HEX,x
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sta (+) +1
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sty (+) +2
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lda $sourceName
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+ sta ${'$'}ffff ; modified
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""")
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storeByteViaRegisterAInMemoryAddress(sourceName, target.memoryAddress)
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}
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}
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}
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@ -313,7 +320,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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internal fun assignFromRegister(target: AssignTarget, register: CpuRegister) {
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private fun assignFromRegister(target: AssignTarget, register: CpuRegister) {
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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when {
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@ -372,7 +379,39 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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private fun storeByteViaRegisterAInMemoryAddress(ldaInstructionArg: String, memoryAddress: DirectMemoryWrite) {
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val addressExpr = memoryAddress.addressExpression
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val addressLv = addressExpr as? NumericLiteralValue
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when {
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addressLv != null -> asmgen.out(" lda $ldaInstructionArg | sta ${addressLv.number.toHex()}")
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addressExpr is IdentifierReference -> {
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val targetName = asmgen.asmIdentifierName(addressExpr)
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asmgen.out("""
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lda $targetName
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sta ${C64Zeropage.SCRATCH_W1}
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lda $targetName+1
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sta ${C64Zeropage.SCRATCH_W1+1}
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lda $ldaInstructionArg
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ldy #0
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sta (${C64Zeropage.SCRATCH_W1}),y""")
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}
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else -> {
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asmgen.translateExpression(addressExpr)
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asmgen.out("""
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inx
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lda $ESTACK_LO_HEX,x
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sta ${C64Zeropage.SCRATCH_W1}
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lda $ESTACK_HI_HEX,x
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sta ${C64Zeropage.SCRATCH_W1+1}
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lda $ldaInstructionArg
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ldy #0
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sta (${C64Zeropage.SCRATCH_W1}),y""")
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}
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}
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}
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private fun storeRegisterInMemoryAddress(register: CpuRegister, memoryAddress: DirectMemoryWrite) {
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// this is optimized for register A.
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val addressExpr = memoryAddress.addressExpression
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val addressLv = addressExpr as? NumericLiteralValue
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val registerName = register.name.toLowerCase()
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@ -381,48 +420,35 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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addressExpr is IdentifierReference -> {
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val targetName = asmgen.asmIdentifierName(addressExpr)
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when (register) {
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CpuRegister.A -> asmgen.out("""
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ldy $targetName
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sty (+) +1
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ldy $targetName+1
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sty (+) +2
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+ sta ${'$'}ffff ; modified""")
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CpuRegister.X -> asmgen.out("""
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ldy $targetName
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sty (+) +1
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ldy $targetName+1
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sty (+) +2
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+ stx ${'$'}ffff ; modified""")
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CpuRegister.Y -> asmgen.out("""
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lda $targetName
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sta (+) +1
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lda $targetName+1
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sta (+) +2
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+ sty ${'$'}ffff ; modified""")
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CpuRegister.A -> {}
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CpuRegister.X -> asmgen.out(" txa")
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CpuRegister.Y -> asmgen.out(" tya")
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}
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asmgen.out("""
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ldy $targetName
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sty ${C64Zeropage.SCRATCH_W1}
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ldy $targetName+1
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sty ${C64Zeropage.SCRATCH_W1+1}
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ldy #0
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sta (${C64Zeropage.SCRATCH_W1}),y""")
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}
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else -> {
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asmgen.saveRegister(register)
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asmgen.translateExpression(addressExpr)
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asmgen.restoreRegister(register)
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when (register) {
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CpuRegister.A -> asmgen.out(" tay")
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CpuRegister.X -> throw AssemblyError("can't use X register here")
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CpuRegister.Y -> {}
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}
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asmgen.restoreRegister(CpuRegister.A)
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asmgen.out("""
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inx
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lda $ESTACK_LO_HEX,x
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sta (+) +1
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lda $ESTACK_HI_HEX,x
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sta (+) +2
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+ sty ${'$'}ffff ; modified
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""")
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inx
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ldy $ESTACK_LO_HEX,x
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sty ${C64Zeropage.SCRATCH_W1}
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ldy $ESTACK_HI_HEX,x
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sty ${C64Zeropage.SCRATCH_W1+1}
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ldy #0
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sta (${C64Zeropage.SCRATCH_W1}),y""")
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}
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}
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}
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internal fun assignFromWordConstant(target: AssignTarget, word: Int) {
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private fun assignFromWordConstant(target: AssignTarget, word: Int) {
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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when {
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@ -467,17 +493,17 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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internal fun assignFromByteConstant(target: AssignTarget, byte: Short) {
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private fun assignFromByteConstant(target: AssignTarget, byte: Short) {
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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val targetMemory = target.memoryAddress
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when {
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targetIdent != null -> {
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val targetName = asmgen.asmIdentifierName(targetIdent)
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asmgen.out(" lda #${byte.toHex()} | sta $targetName ")
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}
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target.memoryAddress != null -> {
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asmgen.out(" ldy #${byte.toHex()}")
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storeRegisterInMemoryAddress(CpuRegister.Y, target.memoryAddress)
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targetMemory != null -> {
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storeByteViaRegisterAInMemoryAddress("#${byte.toHex()}", targetMemory)
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}
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targetArrayIdx != null -> {
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val index = targetArrayIdx.arrayspec.index
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@ -495,7 +521,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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internal fun assignFromFloatConstant(target: AssignTarget, float: Double) {
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private fun assignFromFloatConstant(target: AssignTarget, float: Double) {
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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if (float == 0.0) {
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@ -594,7 +620,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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}
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}
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internal fun assignFromMemoryByte(target: AssignTarget, address: Int?, identifier: IdentifierReference?) {
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private fun assignFromMemoryByte(target: AssignTarget, address: Int?, identifier: IdentifierReference?) {
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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if (address != null) {
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@ -607,8 +633,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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""")
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}
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target.memoryAddress != null -> {
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asmgen.out(" ldy ${address.toHex()}")
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storeRegisterInMemoryAddress(CpuRegister.Y, target.memoryAddress)
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storeByteViaRegisterAInMemoryAddress(address.toHex(), target.memoryAddress)
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}
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targetArrayIdx != null -> {
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val index = targetArrayIdx.arrayspec.index
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@ -631,8 +656,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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sta $targetName""")
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}
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target.memoryAddress != null -> {
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asmgen.out(" ldy $sourceName")
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storeRegisterInMemoryAddress(CpuRegister.Y, target.memoryAddress)
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storeByteViaRegisterAInMemoryAddress(sourceName, target.memoryAddress)
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}
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targetArrayIdx != null -> {
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val index = targetArrayIdx.arrayspec.index
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@ -663,13 +687,4 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
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throw AssemblyError("weird array type")
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}
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}
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fun assignToRegister(reg: CpuRegister, value: Short?, identifier: IdentifierReference?) {
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if(value!=null) {
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asmgen.out(" ld${reg.toString().toLowerCase()} #${value.toHex()}")
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} else if(identifier!=null) {
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val name = asmgen.asmIdentifierName(identifier)
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asmgen.out(" ld${reg.toString().toLowerCase()} $name")
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}
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}
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}
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@ -140,10 +140,11 @@ internal class ExpressionsAsmGen(private val program: Program, private val asmge
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val sourceName = asmgen.asmIdentifierName(expr.addressExpression as IdentifierReference)
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asmgen.out("""
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||||
lda $sourceName
|
||||
sta (+) +1
|
||||
sta ${C64MachineDefinition.C64Zeropage.SCRATCH_W1}
|
||||
lda $sourceName+1
|
||||
sta (+) +2
|
||||
+ lda ${'$'}ffff ; modified
|
||||
sta ${C64MachineDefinition.C64Zeropage.SCRATCH_W1+1}
|
||||
ldy #0
|
||||
lda (${C64MachineDefinition.C64Zeropage.SCRATCH_W1}),y
|
||||
sta $ESTACK_LO_HEX,x
|
||||
dex""")
|
||||
}
|
||||
|
||||
@ -5,6 +5,7 @@ import prog8.ast.Program
|
||||
import prog8.ast.base.*
|
||||
import prog8.ast.expressions.*
|
||||
import prog8.ast.statements.AssignTarget
|
||||
import prog8.ast.statements.Assignment
|
||||
import prog8.ast.statements.Subroutine
|
||||
import prog8.ast.statements.SubroutineParameter
|
||||
import prog8.compiler.AssemblyError
|
||||
@ -107,48 +108,9 @@ internal class FunctionCallAsmGen(private val program: Program, private val asmg
|
||||
val paramVar = parameter.value
|
||||
val scopedParamVar = (sub.scopedname+"."+paramVar.name).split(".")
|
||||
val target = AssignTarget(IdentifierReference(scopedParamVar, sub.position), null, null, sub.position)
|
||||
target.linkParents(value.parent)
|
||||
when (value) {
|
||||
is NumericLiteralValue -> {
|
||||
// optimize when the argument is a constant literal
|
||||
when(parameter.value.type) {
|
||||
in ByteDatatypes -> asmgen.assignFromByteConstant(target, value.number.toShort())
|
||||
in WordDatatypes -> asmgen.assignFromWordConstant(target, value.number.toInt())
|
||||
DataType.FLOAT -> asmgen.assignFromFloatConstant(target, value.number.toDouble())
|
||||
else -> throw AssemblyError("weird parameter datatype")
|
||||
}
|
||||
}
|
||||
is IdentifierReference -> {
|
||||
// optimize when the argument is a variable
|
||||
when (parameter.value.type) {
|
||||
in ByteDatatypes -> asmgen.assignFromByteVariable(target, value)
|
||||
in WordDatatypes -> asmgen.assignFromWordVariable(target, value)
|
||||
DataType.FLOAT -> asmgen.assignFromFloatVariable(target, value)
|
||||
in PassByReferenceDatatypes -> asmgen.assignFromAddressOf(target, value)
|
||||
else -> throw AssemblyError("weird parameter datatype")
|
||||
}
|
||||
}
|
||||
is DirectMemoryRead -> {
|
||||
when(value.addressExpression) {
|
||||
is NumericLiteralValue -> {
|
||||
val address = (value.addressExpression as NumericLiteralValue).number.toInt()
|
||||
asmgen.assignFromMemoryByte(target, address, null)
|
||||
}
|
||||
is IdentifierReference -> {
|
||||
asmgen.assignFromMemoryByte(target, null, value.addressExpression as IdentifierReference)
|
||||
}
|
||||
else -> {
|
||||
asmgen.translateExpression(value.addressExpression)
|
||||
asmgen.out(" jsr prog8_lib.read_byte_from_address | inx")
|
||||
asmgen.assignFromRegister(target, CpuRegister.A)
|
||||
}
|
||||
}
|
||||
}
|
||||
else -> {
|
||||
asmgen.translateExpression(value)
|
||||
asmgen.assignFromEvalResult(target)
|
||||
}
|
||||
}
|
||||
val assign = Assignment(target, value, value.position)
|
||||
assign.linkParents(value.parent)
|
||||
asmgen.translate(assign)
|
||||
}
|
||||
|
||||
private fun argumentViaRegister(sub: Subroutine, parameter: IndexedValue<SubroutineParameter>, value: Expression) {
|
||||
|
||||
@ -7,21 +7,10 @@ main {
|
||||
|
||||
sub start() {
|
||||
|
||||
c64scr.print_ub(5)
|
||||
c64.CHROUT('\n')
|
||||
return
|
||||
ubyte A=5
|
||||
uword clr = $d020
|
||||
@(clr+1) = A
|
||||
|
||||
c64scr.print_ub(5)
|
||||
c64.CHROUT('\n')
|
||||
|
||||
goto start
|
||||
|
||||
c64scr.print_ub(5)
|
||||
c64.CHROUT('\n')
|
||||
|
||||
exit(11)
|
||||
|
||||
c64scr.print_ub(5)
|
||||
c64.CHROUT('\n')
|
||||
; uword xx = @(clr+1)
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user