From 6f67fc0e02dcfb7709161e5886dd103cb6385d3b Mon Sep 17 00:00:00 2001 From: Irmen de Jong Date: Thu, 3 Nov 2022 20:17:55 +0100 Subject: [PATCH] ir: get rid of '_' symbol prefix --- .../prog8/codegen/intermediate/IRCodeGen.kt | 36 +++++++++++-------- docs/source/todo.rst | 8 +++-- .../src/prog8/intermediate/IRInstructions.kt | 5 +-- .../src/prog8/intermediate/IRProgram.kt | 2 +- intermediate/src/prog8/intermediate/Utils.kt | 10 ++---- intermediate/test/TestInstructions.kt | 2 +- 6 files changed, 32 insertions(+), 31 deletions(-) diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt index c18f3d9e7..e0c42871e 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt @@ -257,7 +257,9 @@ class IRCodeGen( sub.retvalRegisters, sub.inline, sub.position) - renamedSub.add(sub.children.single()) + + if(sub.children.isNotEmpty()) + renamedSub.add(sub.children.single()) parent.children.remove(sub) parent.add(renamedSub) } @@ -1091,19 +1093,25 @@ class IRCodeGen( irBlock += sub } is PtAsmSub -> { - val assemblyChild = child.children.single() as PtInlineAssembly - val asmChunk = IRInlineAsmChunk( - child.name, assemblyChild.assembly, assemblyChild.isIR, null - ) - irBlock += IRAsmSubroutine( - child.name, - child.address, - child.clobbers, - child.parameters.map { Pair(it.first.type, it.second) }, // note: the name of the asmsub param is not used anymore. - child.returnTypes.zip(child.retvalRegisters), - asmChunk, - child.position - ) + if(child.address!=null) { + // romsub. No codegen needed: calls to this are jumping straight to the address. + require(child.children.isEmpty()) + } else { + // regular asmsub + val assemblyChild = child.children.single() as PtInlineAssembly + val asmChunk = IRInlineAsmChunk( + child.name, assemblyChild.assembly, assemblyChild.isIR, null + ) + irBlock += IRAsmSubroutine( + child.name, + child.address, + child.clobbers, + child.parameters.map { Pair(it.first.type, it.second) }, // note: the name of the asmsub param is not used anymore. + child.returnTypes.zip(child.retvalRegisters), + asmChunk, + child.position + ) + } } is PtInlineAssembly -> { irBlock += IRInlineAsmChunk(null, child.assembly, child.isIR, null) diff --git a/docs/source/todo.rst b/docs/source/todo.rst index 6cbfb7c9a..496cabbf2 100644 --- a/docs/source/todo.rst +++ b/docs/source/todo.rst @@ -3,9 +3,6 @@ TODO For next release ^^^^^^^^^^^^^^^^ -- ir: get rid of '_' label prefix? -- fix expericodegen (ir code gen for regular cx16 target) - ... @@ -21,7 +18,12 @@ Future Things and Ideas Compiler: - create BSS section in output program and put StStaticVariables in there with bss=true. Don't forget to add init code to zero out everything that was put in bss. If array in bss->only zero ONCE! So requires self-modifying code +- ir: mechanism to determine for chunks which registers are getting input values from "outside" +- ir: mechanism to determine for chunks which registers are passing values out? (i.e. are used again in another chunk) +- ir: peephole opt: renumber registers in chunks to start with 1 again every time (but keep entry values in mind!) +- ir peephole opt: reuse registers in chunks (but keep result registers in mind that pass values out!) - ir: add more optimizations in IRPeepholeOptimizer +- ir: write addresses as hex into p8ir file - see if we can let for loops skip the loop if end?, placeholder var labelSymbol: String? = null fun parseValueOrPlaceholder(operand: String, location: Pair?, rest: String, restIndex: Int): Float? { - return if(operand.startsWith('_')) { - labelSymbol = rest.split(",")[restIndex].trim().drop(1) - if(location!=null) - placeholders[location] = labelSymbol!! - null - } else if(operand[0].isLetter()) { + return if(operand[0].isLetter()) { labelSymbol = rest.split(",")[restIndex].trim() if(location!=null) placeholders[location] = labelSymbol!! @@ -229,8 +224,7 @@ fun parseIRCodeLine(line: String, location: Pair?, placeholder floatValue = value if(opcode in OpcodesForCpuRegisters) { - val regStr = rest.split(',').last().lowercase().trim() - val reg = if(regStr.startsWith('_')) regStr.substring(1) else regStr + val reg = rest.split(',').last().lowercase().trim() if(reg !in setOf( "a", "x", "y", "ax", "ay", "xy", diff --git a/intermediate/test/TestInstructions.kt b/intermediate/test/TestInstructions.kt index 6f3ade2e7..72b62925c 100644 --- a/intermediate/test/TestInstructions.kt +++ b/intermediate/test/TestInstructions.kt @@ -43,7 +43,7 @@ class TestInstructions: FunSpec({ ins.reg2 shouldBe null ins.value shouldBe null ins.labelSymbol shouldBe "a.b.c" - ins.toString() shouldBe "bz.w r11,_a.b.c" + ins.toString() shouldBe "bz.w r11,a.b.c" } test("with output registers") {