diff --git a/intermediate/src/prog8/intermediate/IRInstructions.kt b/intermediate/src/prog8/intermediate/IRInstructions.kt index a706f0d7e..7e7f98ec6 100644 --- a/intermediate/src/prog8/intermediate/IRInstructions.kt +++ b/intermediate/src/prog8/intermediate/IRInstructions.kt @@ -97,18 +97,18 @@ bgesr reg1, reg2, address - jump to location in program given by l ble reg1, value, address - jump to location in program given by location, if reg1 <= immediate value (unsigned) bles reg1, value, address - jump to location in program given by location, if reg1 <= immediate value (signed) ( NOTE: there are no bltr/bler instructions because these are equivalent to bgtr/bger with the register operands swapped around.) -sz reg1, reg2 - set reg1=1.b if reg2==0, else 0.b -snz reg1, reg2 - set reg1=1.b if reg2!=0, else 0.b -seq reg1, reg2 - set reg1=1.b if reg1 == reg2, else 0.b -sne reg1, reg2 - set reg1=1.b if reg1 != reg2, else 0.b -slt reg1, reg2 - set reg1=1.b if reg1 < reg2 (unsigned), else 0.b -slts reg1, reg2 - set reg1=1.b if reg1 < reg2 (signed), else 0.b -sle reg1, reg2 - set reg1=1.b if reg1 <= reg2 (unsigned), else 0.b -sles reg1, reg2 - set reg1=1.b if reg1 <= reg2 (signed), else 0.b -sgt reg1, reg2 - set reg1=1.b if reg1 > reg2 (unsigned), else 0.b -sgts reg1, reg2 - set reg1=1.b if reg1 > reg2 (signed), else 0.b -sge reg1, reg2 - set reg1=1.b if reg1 >= reg2 (unsigned), else 0.b -sges reg1, reg2 - set reg1=1.b if reg1 >= reg2 (signed), else 0.b +sz reg1, reg2 - set reg1=-1 (all bits one) if reg2==0, else 0 +snz reg1, reg2 - set reg1=-1 (all bits one) if reg2!=0, else 0 +seq reg1, reg2 - set reg1=-1 (all bits one) if reg1 == reg2, else 0 +sne reg1, reg2 - set reg1=-1 (all bits one) if reg1 != reg2, else 0 +slt reg1, reg2 - set reg1=-1 (all bits one) if reg1 < reg2 (unsigned), else 0 +slts reg1, reg2 - set reg1=-1 (all bits one) if reg1 < reg2 (signed), else 0 +sle reg1, reg2 - set reg1=-1 (all bits one) if reg1 <= reg2 (unsigned), else 0 +sles reg1, reg2 - set reg1=-1 (all bits one) if reg1 <= reg2 (signed), else 0 +sgt reg1, reg2 - set reg1=-1 (all bits one) if reg1 > reg2 (unsigned), else 0 +sgts reg1, reg2 - set reg1=-1 (all bits one) if reg1 > reg2 (signed), else 0 +sge reg1, reg2 - set reg1=-1 (all bits one) if reg1 >= reg2 (unsigned), else 0 +sges reg1, reg2 - set reg1=-1 (all bits one) if reg1 >= reg2 (signed), else 0 ARITHMETIC diff --git a/virtualmachine/src/prog8/vm/VirtualMachine.kt b/virtualmachine/src/prog8/vm/VirtualMachine.kt index 218d2aacd..4b959d098 100644 --- a/virtualmachine/src/prog8/vm/VirtualMachine.kt +++ b/virtualmachine/src/prog8/vm/VirtualMachine.kt @@ -808,77 +808,77 @@ class VirtualMachine(irProgram: IRProgram) { private fun InsSZ(i: IRInstruction) { val (_: Int, right: Int) = getSetOnConditionOperands(i) - val value = if(right==0) 1 else 0 + val value = if(right==0) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc() } private fun InsSNZ(i: IRInstruction) { val (_: Int, right: Int) = getSetOnConditionOperands(i) - val value = if(right!=0) 1 else 0 + val value = if(right!=0) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc() } private fun InsSEQ(i: IRInstruction) { val (left: Int, right: Int) = getSetOnConditionOperands(i) - val value = if(left==right) 1 else 0 + val value = if(left==right) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc() } private fun InsSNE(i: IRInstruction) { val (left: Int, right: Int) = getSetOnConditionOperands(i) - val value = if(left!=right) 1 else 0 + val value = if(left!=right) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc() } private fun InsSLT(i: IRInstruction) { val (left, right) = getSetOnConditionOperandsU(i) - val value = if(leftright) 1 else 0 + val value = if(left>right) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc() } private fun InsSGTS(i: IRInstruction) { val (left, right) = getSetOnConditionOperands(i) - val value = if(left>right) 1 else 0 + val value = if(left>right) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc() } private fun InsSLE(i: IRInstruction) { val (left, right) = getSetOnConditionOperandsU(i) - val value = if(left<=right) 1 else 0 + val value = if(left<=right) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc() } private fun InsSLES(i: IRInstruction) { val (left, right) = getSetOnConditionOperands(i) - val value = if(left<=right) 1 else 0 + val value = if(left<=right) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc() } private fun InsSGE(i: IRInstruction) { val (left, right) = getSetOnConditionOperandsU(i) - val value = if(left>=right) 1 else 0 + val value = if(left>=right) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc() @@ -886,7 +886,7 @@ class VirtualMachine(irProgram: IRProgram) { private fun InsSGES(i: IRInstruction) { val (left, right) = getSetOnConditionOperands(i) - val value = if(left>=right) 1 else 0 + val value = if(left>=right) -1 else 0 setResultReg(i.reg1!!, value, i.type!!) nextPc()