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vm: fix comparison operator codegen for floats
This commit is contained in:
Irmen de Jong
parent
677613d30a
commit
74c05d00a9
@ -316,15 +316,31 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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greaterEquals: Boolean
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): VmCodeChunk {
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val code = VmCodeChunk()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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val ins = if(signed) {
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if(greaterEquals) Opcode.SGES else Opcode.SGTS
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if(vmDt==VmDataType.FLOAT) {
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val leftFpReg = codeGen.vmRegisters.nextFreeFloat()
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val rightFpReg = codeGen.vmRegisters.nextFreeFloat()
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val zeroRegister = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, -1, leftFpReg)
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code += translateExpression(binExpr.right, -1, rightFpReg)
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code += VmCodeInstruction(Opcode.FCOMP, VmDataType.FLOAT, reg1=resultRegister, fpReg1 = leftFpReg, fpReg2 = rightFpReg)
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=zeroRegister, value=0)
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val ins = if (signed) {
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if (greaterEquals) Opcode.SGES else Opcode.SGTS
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} else {
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if (greaterEquals) Opcode.SGE else Opcode.SGT
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}
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code += VmCodeInstruction(ins, VmDataType.BYTE, reg1 = resultRegister, reg2 = resultRegister, reg3 = zeroRegister)
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} else {
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if(greaterEquals) Opcode.SGE else Opcode.SGT
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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val ins = if (signed) {
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if (greaterEquals) Opcode.SGES else Opcode.SGTS
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} else {
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if (greaterEquals) Opcode.SGE else Opcode.SGT
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}
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code += VmCodeInstruction(ins, vmDt, reg1 = resultRegister, reg2 = resultRegister, reg3 = rightResultReg)
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}
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code += VmCodeInstruction(ins, vmDt, reg1=resultRegister, reg2=resultRegister, reg3=rightResultReg)
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return code
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}
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@ -336,25 +352,58 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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lessEquals: Boolean
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): VmCodeChunk {
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val code = VmCodeChunk()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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val ins = if(signed) {
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if(lessEquals) Opcode.SLES else Opcode.SLTS
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if(vmDt==VmDataType.FLOAT) {
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val leftFpReg = codeGen.vmRegisters.nextFreeFloat()
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val rightFpReg = codeGen.vmRegisters.nextFreeFloat()
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val zeroRegister = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, -1, leftFpReg)
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code += translateExpression(binExpr.right, -1, rightFpReg)
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code += VmCodeInstruction(Opcode.FCOMP, VmDataType.FLOAT, reg1=resultRegister, fpReg1 = leftFpReg, fpReg2 = rightFpReg)
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=zeroRegister, value=0)
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val ins = if (signed) {
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if (lessEquals) Opcode.SLES else Opcode.SLTS
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} else {
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if (lessEquals) Opcode.SLE else Opcode.SLT
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}
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code += VmCodeInstruction(ins, VmDataType.BYTE, reg1 = resultRegister, reg2 = resultRegister, reg3 = zeroRegister)
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} else {
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if(lessEquals) Opcode.SLE else Opcode.SLT
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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val ins = if (signed) {
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if (lessEquals) Opcode.SLES else Opcode.SLTS
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} else {
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if (lessEquals) Opcode.SLE else Opcode.SLT
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}
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code += VmCodeInstruction(ins, vmDt, reg1 = resultRegister, reg2 = resultRegister, reg3 = rightResultReg)
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}
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code += VmCodeInstruction(ins, vmDt, reg1=resultRegister, reg2=resultRegister, reg3=rightResultReg)
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return code
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}
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private fun operatorEquals(binExpr: PtBinaryExpression, vmDt: VmDataType, resultRegister: Int, notEquals: Boolean): VmCodeChunk {
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val code = VmCodeChunk()
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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val opcode = if(notEquals) Opcode.SNE else Opcode.SEQ
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code += VmCodeInstruction(opcode, vmDt, reg1=resultRegister, reg2=resultRegister, reg3=rightResultReg)
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if(vmDt==VmDataType.FLOAT) {
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val leftFpReg = codeGen.vmRegisters.nextFreeFloat()
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val rightFpReg = codeGen.vmRegisters.nextFreeFloat()
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code += translateExpression(binExpr.left, -1, leftFpReg)
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code += translateExpression(binExpr.right, -1, rightFpReg)
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code += VmCodeInstruction(Opcode.FCOMP, VmDataType.FLOAT, reg1=resultRegister, fpReg1 = leftFpReg, fpReg2 = rightFpReg)
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if(!notEquals) {
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val label = codeGen.createLabelName()
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code += VmCodeInstruction(Opcode.BZ, VmDataType.BYTE, reg1=resultRegister, symbol = label)
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=resultRegister, value=1)
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code += VmCodeLabel(label)
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val regMask = codeGen.vmRegisters.nextFree()
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=regMask, value=1)
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code += VmCodeInstruction(Opcode.XOR, VmDataType.BYTE, reg1=resultRegister, reg2=resultRegister, reg3=regMask)
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}
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} else {
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val rightResultReg = codeGen.vmRegisters.nextFree()
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code += translateExpression(binExpr.left, resultRegister, -1)
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code += translateExpression(binExpr.right, rightResultReg, -1)
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val opcode = if (notEquals) Opcode.SNE else Opcode.SEQ
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code += VmCodeInstruction(opcode, vmDt, reg1 = resultRegister, reg2 = resultRegister, reg3 = rightResultReg)
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}
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return code
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}
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@ -3,7 +3,6 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- vm: comparison operator codegen with floating point values are wrong?
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- vm: get rid of the 3-register instructions just make them 2 registers? Result register is always same as second?
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- vm: use more instructions in codegen: branching
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- vm: add more instructions operating directly on memory instead of only registers?
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@ -24,44 +24,30 @@ main {
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sub start() {
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ubyte @shared value = inline_candidate()
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value = %01011100
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byte @shared svalue = 99
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svalue = -svalue
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@($5000) = not @($5000)
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sys.set_carry()
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rol(value)
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rol(@($5000))
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txt.print_ub(value)
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txt.nl()
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sys.set_carry()
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ror(value)
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ror(@($5000))
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txt.print_ub(value)
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txt.nl()
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txt.nl()
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value = %01011100
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sys.set_carry()
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rol2(value)
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rol2(@($5000))
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txt.print_ub(value)
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txt.nl()
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sys.clear_carry()
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ror2(value)
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ror2(@($5000))
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txt.print_ub(value)
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txt.nl()
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@($5000) <<= 1
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@($5000) >>= 1
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value <<= 1
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value >>= 1
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txt.print_ub(value)
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txt.nl()
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@($5000) <<= 3
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@($5000) >>= 3
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value <<= 3
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value >>= 3
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txt.print_ub(value)
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txt.nl()
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float fl1 = 1.1
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float fl2 = 2.2
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if fl1==fl2
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txt.print("equals!?\n")
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if fl1!=fl2
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txt.print("not equals.\n")
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fl1 = fl2
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if fl1==fl2
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txt.print("equals.\n")
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if fl1!=fl2
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txt.print("not equals!?\n")
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if fl1 <= fl2
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txt.print("yup\n")
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if fl1 > fl2
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txt.print("nope\n")
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fl1 = 3.3
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if fl1 <= fl2
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txt.print("yup\n")
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if fl1 > fl2
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txt.print("nope\n")
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; txt.print_ub(inline_candidate())
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; txt.nl()
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@ -140,6 +140,7 @@ ftouw reg1, fpreg1 - reg1 = fpreg1 as unsigned word
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ftosw reg1, fpreg1 - reg1 = fpreg1 as signed word
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fpow fpreg1, fpreg2, fpreg3 - fpreg1 = fpreg2 to the power of fpreg3
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fabs fpreg1, fpreg2 - fpreg1 = abs(fpreg2)
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fcomp reg1, fpreg1, fpreg2 - reg1 = result of comparison of fpreg1 and fpreg2: 0=equal, 1=fpreg1 is greater, -1=fpreg1 is smaller
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MISC
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@ -255,6 +256,7 @@ enum class Opcode {
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FROUND,
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FFLOOR,
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FCEIL,
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FCOMP,
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CLC,
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SEC,
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@ -525,6 +527,7 @@ val instructionFormats = mutableMapOf(
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Opcode.FROUND to InstructionFormat.from("F,fr1,fr2"),
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Opcode.FFLOOR to InstructionFormat.from("F,fr1,fr2"),
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Opcode.FCEIL to InstructionFormat.from("F,fr1,fr2"),
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Opcode.FCOMP to InstructionFormat.from("F,r1,fr1,fr2"),
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Opcode.MSIG to InstructionFormat.from("BW,r1,r2"),
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Opcode.PUSH to InstructionFormat.from("BW,r1"),
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@ -188,6 +188,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.FROUND -> InsFROUND(ins)
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Opcode.FFLOOR -> InsFFLOOR(ins)
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Opcode.FCEIL -> InsFCEIL(ins)
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Opcode.FCOMP -> InsFCOMP(ins)
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else -> throw IllegalArgumentException("invalid opcode ${ins.opcode}")
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}
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}
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@ -1141,6 +1142,20 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc++
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}
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private fun InsFCOMP(i: Instruction) {
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val left = registers.getFloat(i.fpReg1!!)
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val right = registers.getFloat(i.fpReg2!!)
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val result =
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if(left<right)
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255u // -1
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else if(left>right)
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1u
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else
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0u
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registers.setUB(i.reg1!!, result.toUByte())
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pc++
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}
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private fun getBranchOperands(i: Instruction): Pair<Int, Int> {
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return when(i.type) {
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VmDataType.BYTE -> Pair(registers.getSB(i.reg1!!).toInt(), registers.getSB(i.reg2!!).toInt())
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