mirror of
https://github.com/irmen/prog8.git
synced 2025-02-25 04:29:36 +00:00
new IR call and return instructions to deal with returnregisters
This commit is contained in:
Irmen de Jong
parent
39132327cc
commit
78a097585d
@ -954,17 +954,13 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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}
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}
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addInstr(result, IRInstruction(Opcode.CALL, labelSymbol=fcall.name), null)
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if(fcall.type==DataType.FLOAT) {
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if (!fcall.void && resultFpRegister != 0) {
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// Call convention: result value is in fr0, so put it in the required register instead.
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addInstr(result, IRInstruction(Opcode.LOADR, IRDataType.FLOAT, fpReg1 = resultFpRegister, fpReg2 = 0), null)
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}
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} else {
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if (!fcall.void && resultRegister != 0) {
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// Call convention: result value is in r0, so put it in the required register instead.
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addInstr(result, IRInstruction(Opcode.LOADR, codeGen.irType(fcall.type), reg1 = resultRegister, reg2 = 0), null)
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}
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if(fcall.void)
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addInstr(result, IRInstruction(Opcode.CALL, labelSymbol=fcall.name), null)
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else {
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if(fcall.type==DataType.FLOAT)
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addInstr(result, IRInstruction(Opcode.CALLRVAL, IRDataType.FLOAT, fpReg1=resultFpRegister, labelSymbol=fcall.name), null)
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else
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addInstr(result, IRInstruction(Opcode.CALLRVAL, codeGen.irType(fcall.type), reg1=resultRegister, labelSymbol=fcall.name), null)
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}
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return result
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}
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@ -983,6 +979,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addInstr(result, IRInstruction(Opcode.STORECPU, paramDt, reg1 = argReg, labelSymbol = paramRegStr), null)
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}
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}
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// just a regular call without using Vm register call convention: the value is returned in CPU registers!
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addInstr(result, IRInstruction(Opcode.CALL, value=callTarget.address.toInt()), null)
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if(!fcall.void) {
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when(callTarget.returns.size) {
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@ -68,6 +68,7 @@ class IRCodeGen(
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}
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if(options.optimize) {
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// TODO integrate into peephole optimizer above
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val opt = IROptimizer(irProg)
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opt.optimize()
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}
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@ -1265,14 +1266,20 @@ class IRCodeGen(
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private fun translate(ret: PtReturn): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val value = ret.value
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if(value!=null) {
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// Call Convention: return value is always returned in r0 (or fr0 if float)
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result += if(value.type==DataType.FLOAT)
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expressionEval.translateExpression(value, -1, 0)
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else
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expressionEval.translateExpression(value, 0, -1)
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if(value==null) {
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addInstr(result, IRInstruction(Opcode.RETURN), null)
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} else {
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if(value.type==DataType.FLOAT) {
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val reg = registers.nextFreeFloat()
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result += expressionEval.translateExpression(value, -1, reg)
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addInstr(result, IRInstruction(Opcode.RETURNREG, IRDataType.FLOAT, fpReg1 = reg), null)
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}
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else {
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val reg = registers.nextFree()
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result += expressionEval.translateExpression(value, reg, -1)
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addInstr(result, IRInstruction(Opcode.RETURNREG, irType(value.type) , reg1=reg), null)
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}
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}
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addInstr(result, IRInstruction(Opcode.RETURN), null)
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return result
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}
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@ -175,7 +175,7 @@ internal class IRPeepholeOptimizer(private val irprog: IRProgram) {
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}
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}
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// remove useless RETURN
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if(ins.opcode == Opcode.RETURN && idx>0) {
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if(idx>0 && (ins.opcode == Opcode.RETURN || ins.opcode==Opcode.RETURNREG)) {
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val previous = chunk.instructions[idx-1] as? IRInstruction
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if(previous?.opcode in OpcodesThatJump) {
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chunk.instructions.removeAt(idx)
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@ -5,6 +5,7 @@ import prog8.intermediate.SyscallRegisterBase
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internal class RegisterPool {
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// reserve 0,1,2 for return values of subroutine calls and syscalls
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// TODO set this back to 0 once 'resultRegister' has been removed everywhere?
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private var firstFree: Int=3
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private var firstFreeFloat: Int=3
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@ -2,6 +2,8 @@ package prog8.iroptimizer
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import prog8.intermediate.*
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// TODO integrate into peephole optimizer
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internal class IROptimizer(val program: IRProgram) {
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fun optimize() {
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program.blocks.forEach { block ->
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@ -36,7 +38,7 @@ internal class IROptimizer(val program: IRProgram) {
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val i1 = first.value
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val i2 = second.value
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// replace call + return --> jump
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if(i1.opcode==Opcode.CALL && i2.opcode==Opcode.RETURN) {
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if((i1.opcode==Opcode.CALL || i1.opcode==Opcode.CALLRVAL) && i2.opcode==Opcode.RETURN) {
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elt.instructions[first.index] = IRInstruction(Opcode.JUMP, value=i1.value, labelSymbol = i1.labelSymbol, branchTarget = i1.branchTarget)
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elt.instructions[second.index] = IRInstruction(Opcode.NOP)
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if(second.index==elt.instructions.size-1) {
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@ -198,7 +198,7 @@ sub str2uword(str string) -> uword {
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%ir {{
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loadm.w r65500,conv.str2uword.string
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syscall 11
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return
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returnreg.w r0
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}}
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}
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@ -209,7 +209,7 @@ sub str2word(str string) -> word {
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%ir {{
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loadm.w r65500,conv.str2word.string
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syscall 12
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return
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returnreg.w r0
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}}
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}
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@ -21,7 +21,7 @@ sub pow(float value, float power) -> float {
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loadm.f fr0,floats.pow.value
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loadm.f fr1,floats.pow.power
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fpow.f fr0,fr1
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return
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returnreg.f fr0
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}}
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}
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@ -29,7 +29,7 @@ sub fabs(float value) -> float {
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%ir {{
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loadm.f fr0,floats.fabs.value
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fabs.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -37,7 +37,7 @@ sub sin(float angle) -> float {
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%ir {{
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loadm.f fr0,floats.sin.angle
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fsin.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -45,7 +45,7 @@ sub cos(float angle) -> float {
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%ir {{
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loadm.f fr0,floats.cos.angle
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fcos.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -53,7 +53,7 @@ sub tan(float value) -> float {
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%ir {{
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loadm.f fr0,floats.tan.value
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ftan.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -61,7 +61,7 @@ sub atan(float value) -> float {
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%ir {{
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loadm.f fr0,floats.atan.value
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fatan.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -69,7 +69,7 @@ sub ln(float value) -> float {
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%ir {{
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loadm.f fr0,floats.ln.value
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fln.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -77,7 +77,7 @@ sub log2(float value) -> float {
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%ir {{
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loadm.f fr0,floats.log2.value
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flog.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -85,7 +85,7 @@ sub sqrt(float value) -> float {
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%ir {{
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loadm.f fr0,floats.sqrt.value
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sqrt.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -103,7 +103,7 @@ sub round(float value) -> float {
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%ir {{
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loadm.f fr0,floats.round.value
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fround.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -111,7 +111,7 @@ sub floor(float value) -> float {
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%ir {{
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loadm.f fr0,floats.floor.value
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ffloor.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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@ -120,14 +120,14 @@ sub ceil(float value) -> float {
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%ir {{
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loadm.f fr0,floats.ceil.value
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fceil.f fr0,fr0
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return
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returnreg.f fr0
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}}
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}
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sub rndf() -> float {
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%ir {{
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syscall 35
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return
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returnreg.f fr0
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}}
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}
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@ -162,14 +162,14 @@ math {
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sub rnd() -> ubyte {
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%ir {{
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syscall 33
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return
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returnreg.b r0
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}}
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}
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sub rndw() -> uword {
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%ir {{
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syscall 34
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return
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returnreg.w r0
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}}
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}
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@ -87,7 +87,7 @@ string {
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loadm.w r65500,string.compare.st1
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loadm.w r65501,string.compare.st2
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syscall 29
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return
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returnreg.b r0
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}}
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}
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@ -108,7 +108,7 @@ sys {
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loadm.w r65500,sys.gfx_getpixel.xx
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loadm.w r65501,sys.gfx_getpixel.yy
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syscall 30
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return
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returnreg.b r0
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}}
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}
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}
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@ -124,7 +124,7 @@ sub input_chars (uword buffer) -> ubyte {
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%ir {{
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loadm.w r65500,txt.input_chars.buffer
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syscall 6
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return
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returnreg.b r0
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}}
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}
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@ -3,9 +3,7 @@ TODO
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For next minor release
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^^^^^^^^^^^^^^^^^^^^^^
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- IR: don't hardcode r0/fr0 as return registers.
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instead have RETURN -> returns void, RETURNREG <register> -> return value from given register
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also CALL -> void call, CALLRVAL -> specify register to put call result in. CALLRVAL r0, functionThatReturnsInt
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- get rid of ResultRegister in IR codegen? as the calls now encode this into the new opcodes...
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...
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@ -47,17 +47,13 @@ storezx reg1, address - store zero at memory address, indexed by
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CONTROL FLOW
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------------
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Possible subroutine call convention:
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Set parameters in Reg 0, 1, 2... before call. Return value set in Reg 0 before return.
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But you can decide whatever you want because here we just care about jumping and returning the flow of control.
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Saving/restoring registers is possible with PUSH and POP instructions.
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jump location - continue running at instruction number given by location
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jumpa address - continue running at memory address (note: only used to encode a physical cpu jump to fixed address instruction)
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call location - save current instruction location+1, continue execution at instruction nr given by location
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calli reg1 - save current instruction location+1, continue execution at instruction number in reg1
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call location - save current instruction location+1, continue execution at instruction nr given by location. Expect no return value.
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callrval reg1, location - like call but expects a return value from a returnreg instruction, and puts that in reg1
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syscall value - do a systemcall identified by call number
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return - restore last saved instruction location and continue at that instruction
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return - restore last saved instruction location and continue at that instruction. No return value.
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returnreg reg1 - like return, but also returns a value to the caller via reg1
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BRANCHING and CONDITIONALS
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@ -232,8 +228,10 @@ enum class Opcode {
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JUMP,
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JUMPA,
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CALL,
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CALLRVAL,
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SYSCALL,
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RETURN,
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RETURNREG,
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BSTCC,
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BSTCS,
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@ -363,14 +361,17 @@ enum class Opcode {
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val OpcodesThatJump = setOf(
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Opcode.JUMP,
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Opcode.JUMPA,
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Opcode.RETURN
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Opcode.RETURN,
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Opcode.RETURNREG
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)
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val OpcodesThatBranch = setOf(
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Opcode.JUMP,
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Opcode.JUMPA,
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Opcode.RETURN,
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Opcode.RETURNREG,
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Opcode.CALL,
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Opcode.CALLRVAL,
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Opcode.SYSCALL,
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Opcode.BSTCC,
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Opcode.BSTCS,
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@ -412,6 +413,7 @@ val OpcodesWithMemoryAddressAsValue = setOf(
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Opcode.JUMP,
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Opcode.JUMPA,
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Opcode.CALL,
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Opcode.CALLRVAL,
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Opcode.BSTCC,
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Opcode.BSTCS,
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Opcode.BSTEQ,
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@ -551,8 +553,10 @@ val instructionFormats = mutableMapOf(
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Opcode.JUMP to InstructionFormat.from("N,<v"),
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Opcode.JUMPA to InstructionFormat.from("N,<v"),
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Opcode.CALL to InstructionFormat.from("N,<v"),
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Opcode.CALLRVAL to InstructionFormat.from("BW,<r1,<v | F,<fr1,<v"),
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Opcode.SYSCALL to InstructionFormat.from("N,<v"),
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Opcode.RETURN to InstructionFormat.from("N"),
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Opcode.RETURNREG to InstructionFormat.from("BW,<r1 | F,<fr1"),
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Opcode.BSTCC to InstructionFormat.from("N,<v"),
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Opcode.BSTCS to InstructionFormat.from("N,<v"),
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Opcode.BSTEQ to InstructionFormat.from("N,<v"),
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@ -134,7 +134,7 @@ class IRProgram(val name: String,
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// link all jump and branching instructions to their target
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chunk.instructions.forEach {
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if(it.opcode in OpcodesThatBranch && it.opcode!=Opcode.RETURN && it.labelSymbol!=null)
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if(it.opcode in OpcodesThatBranch && it.opcode!=Opcode.RETURN && it.opcode!=Opcode.RETURNREG && it.labelSymbol!=null)
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it.branchTarget = labeledChunks.getValue(it.labelSymbol)
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// note: branches with an address value cannot be linked to something...
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}
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@ -31,10 +31,11 @@ class BreakpointException(val pcChunk: IRCodeChunk, val pcIndex: Int): Exception
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@Suppress("FunctionName")
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class VirtualMachine(irProgram: IRProgram) {
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class CallSiteContext(val returnChunk: IRCodeChunk, val returnIndex: Int, val returnValueReg: Int?, val returnValueFpReg: Int?)
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val memory = Memory()
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val program: List<IRCodeChunk>
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val registers = Registers()
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val callStack = Stack<Pair<IRCodeChunk, Int>>()
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val callStack = Stack<CallSiteContext>()
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val valueStack = Stack<UByte>() // max 128 entries
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var breakpointHandler: ((pcChunk: IRCodeChunk, pcIndex: Int) -> Unit)? = null // can set custom breakpoint handler
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var pcChunk = IRCodeChunk(null, null)
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@ -170,8 +171,10 @@ class VirtualMachine(irProgram: IRProgram) {
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Opcode.JUMP -> InsJUMP(ins)
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Opcode.JUMPA -> throw IllegalArgumentException("vm program can't jump to system memory address (JUMPA)")
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Opcode.CALL -> InsCALL(ins)
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Opcode.CALLRVAL -> InsCALLRVAL(ins)
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Opcode.SYSCALL -> InsSYSCALL(ins)
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Opcode.RETURN -> InsRETURN()
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Opcode.RETURNREG -> InsRETURNREG(ins)
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Opcode.BSTCC -> InsBSTCC(ins)
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Opcode.BSTCS -> InsBSTCS(ins)
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Opcode.BSTEQ -> InsBSTEQ(ins)
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@ -578,7 +581,12 @@ class VirtualMachine(irProgram: IRProgram) {
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}
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private fun InsCALL(i: IRInstruction) {
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callStack.push(Pair(pcChunk, pcIndex+1))
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callStack.push(CallSiteContext(pcChunk, pcIndex+1, null, null))
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branchTo(i)
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}
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private fun InsCALLRVAL(i: IRInstruction) {
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callStack.push(CallSiteContext(pcChunk, pcIndex+1, i.reg1, i.fpReg1))
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branchTo(i)
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}
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@ -586,9 +594,49 @@ class VirtualMachine(irProgram: IRProgram) {
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if(callStack.isEmpty())
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exit(0)
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else {
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val (chunk, idx) = callStack.pop()
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pcChunk = chunk
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pcIndex = idx
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val context = callStack.pop()
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pcChunk = context.returnChunk
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pcIndex = context.returnIndex
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// ignore any return values.
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}
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}
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private fun InsRETURNREG(i: IRInstruction) {
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if(callStack.isEmpty())
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exit(0)
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else {
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val context = callStack.pop()
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when (i.type!!) {
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IRDataType.BYTE -> {
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if(context.returnValueReg!=null)
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registers.setUB(context.returnValueReg, registers.getUB(i.reg1!!))
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else {
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val callInstr = context.returnChunk.instructions[context.returnIndex-1]
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if(callInstr.opcode!=Opcode.CALL)
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throw IllegalArgumentException("missing return value reg")
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}
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}
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IRDataType.WORD -> {
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if(context.returnValueReg!=null)
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registers.setUW(context.returnValueReg, registers.getUW(i.reg1!!))
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else {
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val callInstr = context.returnChunk.instructions[context.returnIndex-1]
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if(callInstr.opcode!=Opcode.CALL)
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throw IllegalArgumentException("missing return value reg")
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}
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}
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IRDataType.FLOAT -> {
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if(context.returnValueFpReg!=null)
|
||||
registers.setFloat(context.returnValueFpReg, registers.getFloat(i.fpReg1!!))
|
||||
else {
|
||||
val callInstr = context.returnChunk.instructions[context.returnIndex-1]
|
||||
if(callInstr.opcode!=Opcode.CALL)
|
||||
throw IllegalArgumentException("missing return value reg")
|
||||
}
|
||||
}
|
||||
}
|
||||
pcChunk = context.returnChunk
|
||||
pcIndex = context.returnIndex
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user