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generate 65c02 TSB/TRB instructions in certain cases

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Irmen de Jong
2024-07-16 00:25:29 +02:00
parent d5adb85e5b
commit 78c7ee247a
4 changed files with 67 additions and 48 deletions
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docs/source/todo.rst
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@@ -91,7 +91,6 @@ Libraries:
Optimizations:
- For 65c02 targets: use trb and tsb instructions if possible (f.ex. generating ``lda cmask trb nvub`` for ``nvub &= ~cmask`` and ``lda cmask and fillm tsb nvub`` for ``nvub |= cmask & fillm``
- VariableAllocator: can we think of a smarter strategy for allocating variables into zeropage, rather than first-come-first-served?
for instance, vars used inside loops first, then loopvars, then uwords used as pointers, then the rest
- various optimizers skip stuff if compTarget.name==VMTarget.NAME. Once 6502-codegen is done from IR code,