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optimize trivial 65c02 stack instructions
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Irmen de Jong
parent
1c97c22eff
commit
7a9dd1ac9b
@ -384,6 +384,7 @@ private fun optimizeStoreLoadSame(
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for (lines in linesByFour) {
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val first = lines[1].value.trimStart()
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val second = lines[2].value.trimStart()
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val third = lines[3].value.trimStart()
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// sta X + lda X, sty X + ldy X, stx X + ldx X -> the second instruction can OFTEN be eliminated
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if ((first.startsWith("sta ") && second.startsWith("lda ")) ||
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@ -393,7 +394,6 @@ private fun optimizeStoreLoadSame(
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(first.startsWith("ldy ") && second.startsWith("ldy ")) ||
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(first.startsWith("ldx ") && second.startsWith("ldx "))
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) {
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val third = lines[3].value.trimStart()
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val attemptRemove =
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if(third.isBranch()) {
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// a branch instruction follows, we can only remove the load instruction if
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@ -446,6 +446,23 @@ private fun optimizeStoreLoadSame(
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if (firstLoc == secondLoc)
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mods.add(Modification(lines[2].index, true, null))
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}
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// phy + ldy + pla -> tya + ldy
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// phx + ldx + pla -> txa + ldx
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// pha + lda + pla -> nop
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if(first=="phy" && second.startsWith("ldy ") && third=="pla") {
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mods.add(Modification(lines[3].index, true, null))
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mods.add(Modification(lines[1].index, false, " tya"))
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}
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else if(first=="phx" && second.startsWith("ldx ") && third=="pla") {
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mods.add(Modification(lines[3].index, true, null))
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mods.add(Modification(lines[1].index, false, " txa"))
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}
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else if(first=="pha" && second.startsWith("lda ") && third=="pla") {
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mods.add(Modification(lines[1].index, true, null))
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mods.add(Modification(lines[2].index, true, null))
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mods.add(Modification(lines[3].index, true, null))
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}
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}
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return mods
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}
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@ -3182,11 +3182,20 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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else {
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if (regs !in Cx16VirtualRegisters) {
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when (regs) {
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RegisterOrPair.AX -> asmgen.out(" pha | txa | pha")
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RegisterOrPair.AY -> asmgen.out(" pha | tya | pha")
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RegisterOrPair.XY -> asmgen.out(" txa | pha | tya | pha")
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else -> throw AssemblyError("expected reg pair")
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if (asmgen.isTargetCpu(CpuType.CPU65c02)) {
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when (regs) {
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RegisterOrPair.AX -> asmgen.out(" pha | phx")
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RegisterOrPair.AY -> asmgen.out(" pha | phy")
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RegisterOrPair.XY -> asmgen.out(" phx | phy")
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else -> throw AssemblyError("expected reg pair")
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}
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} else {
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when (regs) {
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RegisterOrPair.AX -> asmgen.out(" pha | txa | pha")
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RegisterOrPair.AY -> asmgen.out(" pha | tya | pha")
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RegisterOrPair.XY -> asmgen.out(" txa | pha | tya | pha")
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else -> throw AssemblyError("expected reg pair")
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}
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}
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asmgen.loadScaledArrayIndexIntoRegister(target.array, CpuRegister.Y)
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asmgen.out("""
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@ -3225,11 +3234,20 @@ internal class AssignmentAsmGen(private val program: PtProgram,
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}
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else {
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if (regs !in Cx16VirtualRegisters) {
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when (regs) {
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RegisterOrPair.AX -> asmgen.out(" pha | txa | pha")
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RegisterOrPair.AY -> asmgen.out(" pha | tya | pha")
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RegisterOrPair.XY -> asmgen.out(" txa | pha | tya | pha")
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else -> throw AssemblyError("expected reg pair")
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if (asmgen.isTargetCpu(CpuType.CPU65c02)) {
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when (regs) {
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RegisterOrPair.AX -> asmgen.out(" pha | phx")
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RegisterOrPair.AY -> asmgen.out(" pha | phy")
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RegisterOrPair.XY -> asmgen.out(" phx | phy")
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else -> throw AssemblyError("expected reg pair")
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}
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} else {
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when (regs) {
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RegisterOrPair.AX -> asmgen.out(" pha | txa | pha")
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RegisterOrPair.AY -> asmgen.out(" pha | tya | pha")
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RegisterOrPair.XY -> asmgen.out(" txa | pha | tya | pha")
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else -> throw AssemblyError("expected reg pair")
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}
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}
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asmgen.loadScaledArrayIndexIntoRegister(target.array, CpuRegister.Y)
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asmgen.out("""
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@ -6,8 +6,6 @@ causes compiler error for virtual: just calling txt.cls() gives compile error un
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https://github.com/irmen/prog8/issues/136 (string.find register order issue)
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optimization: for 65c02 sometimes tya pha is generated, could be just phy (mind if A gets used afterwards though!) (same for pla tay etcetera?)
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if-optimization:
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if row == NUMQUEENS {
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print_solution()
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157
examples/test.p8
157
examples/test.p8
@ -1,133 +1,52 @@
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%import math
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%import textio
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%zeropage basicsafe
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%option no_sysinit
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main {
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sub start() {
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cx16.r0sL = 127
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cx16.r0sL = bytefunc(cx16.r0sL+1)
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cx16.r0sL = 0
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cx16.r0sL = bytefunc(cx16.r0sL-1)
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cx16.r0sL = 55
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cx16.r0sL = bytefunc(cx16.r0sL+20)
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cx16.r0sL = 55
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cx16.r0sL = bytefunc(cx16.r0sL-20)
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cx16.r0s = $99ff as word
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cx16.r0s = wordfunc(cx16.r0s+1)
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cx16.r0s = $9900 as word
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cx16.r0s = wordfunc(cx16.r0s-1)
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cx16.r0s = -12345
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cx16.r0s = wordfunc(cx16.r0s+100)
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cx16.r0s = -12345
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cx16.r0s = wordfunc(cx16.r0s-100)
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signed()
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unsigned()
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}
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sub signed() {
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byte @shared bvalue = -100
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word @shared wvalue = -20000
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sub bytefunc(byte x) -> byte {
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txt.print_ubhex(x as ubyte, true)
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txt.spc()
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txt.print_b(x)
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bvalue /= 2 ; TODO should be a simple bit shift?
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wvalue /= 2 ; TODO should be a simple bit shift?
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txt.print_b(bvalue)
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txt.nl()
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txt.print_w(wvalue)
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txt.nl()
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bvalue *= 2
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wvalue *= 2
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txt.print_b(bvalue)
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txt.nl()
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txt.print_w(wvalue)
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txt.nl()
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return x
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}
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sub wordfunc(word x) -> word {
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txt.print_uwhex(x as uword, true)
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txt.spc()
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txt.print_w(x)
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sub unsigned() {
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ubyte @shared ubvalue = 100
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uword @shared uwvalue = 20000
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ubvalue /= 2
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uwvalue /= 2
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txt.print_ub(ubvalue)
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txt.nl()
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txt.print_uw(uwvalue)
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txt.nl()
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ubvalue *= 2
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uwvalue *= 2
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txt.print_ub(ubvalue)
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txt.nl()
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txt.print_uw(uwvalue)
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txt.nl()
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return x
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}
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}
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;%import math
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;%import sprites
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;
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;main {
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; word[128] @split xpos_orig
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; word[128] @split ypos_orig
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; word[128] xpos
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; word[128] ypos
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; ubyte[128] tt
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;
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; sub start() {
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; cx16.mouse_config2(1)
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; sprites.set_mousepointer_hand()
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; ubyte sprdat_bank
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; uword sprdat_addr
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; sprdat_bank, sprdat_addr = sprites.get_data_ptr(0)
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;
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; ubyte sprite
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; for sprite in 0 to 127 {
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; sprites.init(sprite, sprdat_bank, sprdat_addr, sprites.SIZE_16, sprites.SIZE_16, sprites.COLORS_256, 0)
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; xpos_orig[sprite] = sprite*$0003 +100 as word
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; ypos_orig[sprite] = sprite*$0002 +100 as word
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; tt[sprite] = math.rnd()
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; }
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;
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; repeat {
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; sys.waitvsync()
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; sprites.pos_batch(0, 128, &xpos, &ypos)
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; for sprite in 0 to 127 {
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; tt[sprite]++
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; xpos[sprite] = xpos_orig[sprite] + math.sin8(tt[sprite])
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; ypos[sprite] = ypos_orig[sprite] + math.cos8(tt[sprite])
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; }
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; }
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; }
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;}
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;
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;
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;;%import textio
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;;%zeropage basicsafe
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;;%option no_sysinit
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;;
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;;main {
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;; sub start() {
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;; signed()
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;; unsigned()
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;; }
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;;
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;; sub signed() {
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;; byte @shared bvalue = -100
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;; word @shared wvalue = -20000
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;;
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;; bvalue /= 2 ; TODO should be a simple bit shift?
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;; wvalue /= 2 ; TODO should be a simple bit shift?
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;;
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;; txt.print_b(bvalue)
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;; txt.nl()
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;; txt.print_w(wvalue)
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;; txt.nl()
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;;
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;; bvalue *= 2
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;; wvalue *= 2
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;;
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;; txt.print_b(bvalue)
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;; txt.nl()
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;; txt.print_w(wvalue)
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;; txt.nl()
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;; }
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;;
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;; sub unsigned() {
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;; ubyte @shared ubvalue = 100
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;; uword @shared uwvalue = 20000
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;;
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;; ubvalue /= 2
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;; uwvalue /= 2
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;;
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;; txt.print_ub(ubvalue)
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;; txt.nl()
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;; txt.print_uw(uwvalue)
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;; txt.nl()
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;;
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;; ubvalue *= 2
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;; uwvalue *= 2
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;;
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;; txt.print_ub(ubvalue)
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;; txt.nl()
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;; txt.print_uw(uwvalue)
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;; txt.nl()
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;; }
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;;}
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