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Optimize in-place word subtraction and negation

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This commit is contained in:
Natt Akuma 2022-02-04 21:21:06 +07:00
parent 73dfb5f443
commit 7c70c79a84
1 changed files with 31 additions and 35 deletions
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66
codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AugmentableAssignmentAsmGen.kt
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@ -1157,17 +1157,16 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
+""") +""")
else else
asmgen.out(""" asmgen.out("""
ldy #0 ldy #255
lda $otherName lda $otherName
bpl + bpl +
dey ; sign extend iny ; sign extend
+ sty P8ZP_SCRATCH_B1 + eor #255
lda $name
sec sec
sbc $otherName adc $name
sta $name sta $name
lda $name+1 tya
sbc P8ZP_SCRATCH_B1 adc $name+1
sta $name+1""") sta $name+1""")
} }
"*" -> { "*" -> {
@ -1439,29 +1438,28 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
sta $name+1""") sta $name+1""")
} }
"-" -> { "-" -> {
asmgen.assignExpressionToVariable(value, "P8ZP_SCRATCH_REG", valueDt, null) asmgen.assignExpressionToVariable(value, "P8ZP_SCRATCH_B1", valueDt, null)
if(valueDt==DataType.UBYTE) if(valueDt==DataType.UBYTE)
asmgen.out(""" asmgen.out("""
lda $name lda $name
sec sec
sbc P8ZP_SCRATCH_REG sbc P8ZP_SCRATCH_B1
sta $name sta $name
bcs + bcs +
dec $name+1 dec $name+1
+""") +""")
else else
asmgen.out(""" asmgen.out("""
ldy #0 ldy #255
lda P8ZP_SCRATCH_REG lda P8ZP_SCRATCH_B1
bpl + bpl +
dey ; sign extend iny ; sign extend
+ sty P8ZP_SCRATCH_B1 + eor #255
lda $name
sec sec
sbc P8ZP_SCRATCH_REG adc $name
sta $name sta $name
lda $name+1 tya
sbc P8ZP_SCRATCH_B1 adc $name+1
sta $name+1""") sta $name+1""")
} }
"*" -> { "*" -> {
@ -2098,40 +2096,38 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
when(target.register!!) { //P8ZP_SCRATCH_REG when(target.register!!) { //P8ZP_SCRATCH_REG
RegisterOrPair.AX -> { RegisterOrPair.AX -> {
asmgen.out(""" asmgen.out("""
sta P8ZP_SCRATCH_REG
stx P8ZP_SCRATCH_REG+1
lda #0
sec sec
sbc P8ZP_SCRATCH_REG eor #255
adc #0
pha pha
lda #0 txa
sbc P8ZP_SCRATCH_REG+1 eor #255
adc #0
tax tax
pla""") pla""")
} }
RegisterOrPair.AY -> { RegisterOrPair.AY -> {
asmgen.out(""" asmgen.out("""
sta P8ZP_SCRATCH_REG
sty P8ZP_SCRATCH_REG+1
lda #0
sec sec
sbc P8ZP_SCRATCH_REG eor #255
adc #0
pha pha
lda #0 tya
sbc P8ZP_SCRATCH_REG+1 eor #255
adc #0
tay tay
pla""") pla""")
} }
RegisterOrPair.XY -> { RegisterOrPair.XY -> {
asmgen.out(""" asmgen.out("""
stx P8ZP_SCRATCH_REG
sty P8ZP_SCRATCH_REG+1
lda #0
sec sec
sbc P8ZP_SCRATCH_REG txa
eor #255
adc #0
tax tax
lda #0 tya
sbc P8ZP_SCRATCH_REG+1 eor #255
adc #0
tay""") tay""")
} }
in Cx16VirtualRegisters -> throw AssemblyError("cx16 virtual regs should be variables, not real registers") in Cx16VirtualRegisters -> throw AssemblyError("cx16 virtual regs should be variables, not real registers")