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vm/ir: for loop is now correctly skipped if loopvar>endvar

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this is different still in the 6502 codegen, where it wraps around $00!
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Irmen de Jong
2022-12-27 18:12:41 +01:00
parent 81bd5c784e
commit 7ee777f405
4 changed files with 29 additions and 21 deletions
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codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt
+7
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@@ -542,12 +542,19 @@ class IRCodeGen(
result += expressionEval.translateExpression(iterable.to, endvalueReg, -1)
result += expressionEval.translateExpression(iterable.from, indexReg, -1)
val labelAfterFor = createLabelName()
val greaterOpcode = if(loopvarDt in SignedDatatypes) Opcode.BGTS else Opcode.BGT
addInstr(result, IRInstruction(greaterOpcode, loopvarDtIr, indexReg, endvalueReg, labelSymbol=labelAfterFor), null)
addInstr(result, IRInstruction(Opcode.STOREM, loopvarDtIr, reg1=indexReg, labelSymbol=loopvarSymbol), null)
result += labelFirstChunk(translateNode(forLoop.statements), loopLabel)
result += addConstMem(loopvarDtIr, null, loopvarSymbol, step)
addInstr(result, IRInstruction(Opcode.LOADM, loopvarDtIr, reg1 = indexReg, labelSymbol = loopvarSymbol), null)
val branchOpcode = if(loopvarDt in SignedDatatypes) Opcode.BLES else Opcode.BLE
addInstr(result, IRInstruction(branchOpcode, loopvarDtIr, reg1=indexReg, reg2=endvalueReg, labelSymbol=loopLabel), null)
result += IRCodeChunk(labelAfterFor, null)
return result
}