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fix faulty word[x]-- , fix invalid stz addressing modes

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This commit is contained in:
Irmen de Jong 2020-12-24 04:08:52 +01:00
parent 38a6c6a866
commit 80e3a11268
3 changed files with 9 additions and 11 deletions
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2
compiler/src/prog8/compiler/target/c64/codegen/PostIncrDecrAsmGen.kt
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@ -105,7 +105,7 @@ internal class PostIncrDecrAsmGen(private val program: Program, private val asmg
lda $asmArrayvarname,x lda $asmArrayvarname,x
bne + bne +
dec $asmArrayvarname+1,x dec $asmArrayvarname+1,x
+ dec $asmArrayvarname + dec $asmArrayvarname,x
""") """)
} }
DataType.FLOAT -> { DataType.FLOAT -> {

13
compiler/src/prog8/compiler/target/c64/codegen/assignment/AssignmentAsmGen.kt
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@ -1267,11 +1267,12 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
} }
else { else {
asmgen.loadScaledArrayIndexIntoRegister(wordtarget.array!!, wordtarget.datatype, CpuRegister.Y) asmgen.loadScaledArrayIndexIntoRegister(wordtarget.array!!, wordtarget.datatype, CpuRegister.Y)
asmgen.out(" lda $sourceName | sta ${wordtarget.asmVarname},y | iny") asmgen.out("""
if(CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) lda $sourceName
asmgen.out(" stz ${wordtarget.asmVarname},y") sta ${wordtarget.asmVarname},y
else iny
asmgen.out(" lda #0 | sta ${wordtarget.asmVarname},y") lda #0
sta ${wordtarget.asmVarname},y""")
} }
} }
TargetStorageKind.REGISTER -> { TargetStorageKind.REGISTER -> {
@ -1680,7 +1681,7 @@ internal class AssignmentAsmGen(private val program: Program, private val asmgen
} }
else { else {
asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UBYTE, CpuRegister.Y) asmgen.loadScaledArrayIndexIntoRegister(target.array!!, DataType.UBYTE, CpuRegister.Y)
asmgen.out(" stz ${target.asmVarname},y") asmgen.out(" lda #0 | sta ${target.asmVarname},y")
} }
} }
TargetStorageKind.REGISTER -> when(target.register!!) { TargetStorageKind.REGISTER -> when(target.register!!) {

5
compiler/src/prog8/compiler/target/c64/codegen/assignment/AugmentableAssignmentAsmGen.kt
View File

@ -1652,10 +1652,7 @@ internal class AugmentableAssignmentAsmGen(private val program: Program,
} }
TargetStorageKind.ARRAY -> { TargetStorageKind.ARRAY -> {
asmgen.loadScaledArrayIndexIntoRegister(target.array!!, target.datatype, CpuRegister.Y, true) asmgen.loadScaledArrayIndexIntoRegister(target.array!!, target.datatype, CpuRegister.Y, true)
if(CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) asmgen.out(" lda #0 | sta ${target.asmVarname},y")
asmgen.out(" stz ${target.asmVarname},y")
else
asmgen.out(" lda #0 | sta ${target.asmVarname},y")
} }
TargetStorageKind.STACK -> { TargetStorageKind.STACK -> {
if(CompilationTarget.instance.machine.cpu == CpuType.CPU65c02) if(CompilationTarget.instance.machine.cpu == CpuType.CPU65c02)