fix combined reg asm name

This commit is contained in:
Irmen de Jong
2025-10-12 01:34:00 +02:00
parent 424b89f357
commit 8296002887
2 changed files with 2 additions and 2 deletions
@@ -937,7 +937,7 @@ class AsmGen6502Internal (
TargetStorageKind.MEMORY -> throw AssemblyError("memory is bytes not long ${target.position}")
TargetStorageKind.REGISTER -> {
require(target.register in combinedLongRegisters)
val startreg = target.register.toString().take(2).lowercase()
val startreg = target.register!!.startregname()
out("""
lda $valuesym
sta cx16.$startreg
@@ -3301,7 +3301,7 @@ $endLabel""")
TargetStorageKind.MEMORY -> throw AssemblyError("memory is bytes not long ${target.position}")
TargetStorageKind.REGISTER -> {
require(target.register in combinedLongRegisters)
val regstart = target.register.toString().take(2).lowercase()
val regstart = target.register!!.startregname()
when(sourceDt) {
DataType.BYTE -> {
asmgen.out(" lda $varName | sta cx16.$regstart")