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https://github.com/irmen/prog8.git
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IR: fix augmented assignments
This commit is contained in:
Irmen de Jong
parent
befe0fff2a
commit
8c93ec52de
@ -72,25 +72,25 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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private fun assignVarAugmented(symbol: String, assignment: PtAugmentedAssign): IRCodeChunks {
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val value = assignment.value
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val valueVmDt = codeGen.irType(value.type)
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val targetDt = codeGen.irType(assignment.target.type)
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return when (assignment.operator) {
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"+=" -> expressionEval.operatorPlusInplace(null, symbol, valueVmDt, value)
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"-=" -> expressionEval.operatorMinusInplace(null, symbol, valueVmDt, value)
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"*=" -> expressionEval.operatorMultiplyInplace(null, symbol, valueVmDt, value)
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"/=" -> expressionEval.operatorDivideInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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"|=" -> expressionEval.operatorOrInplace(null, symbol, valueVmDt, value)
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"&=" -> expressionEval.operatorAndInplace(null, symbol, valueVmDt, value)
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"^=" -> expressionEval.operatorXorInplace(null, symbol, valueVmDt, value)
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"<<=" -> expressionEval.operatorShiftLeftInplace(null, symbol, valueVmDt, value)
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">>=" -> expressionEval.operatorShiftRightInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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"%=" -> expressionEval.operatorModuloInplace(null, symbol, valueVmDt, value)
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"==" -> expressionEval.operatorEqualsInplace(null, symbol, valueVmDt, value)
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"!=" -> expressionEval.operatorNotEqualsInplace(null, symbol, valueVmDt, value)
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"<" -> expressionEval.operatorLessInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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">" -> expressionEval.operatorGreaterInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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"<=" -> expressionEval.operatorLessEqualInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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">=" -> expressionEval.operatorGreaterEqualInplace(null, symbol, valueVmDt, value.type in SignedDatatypes, value)
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in PrefixOperators -> inplacePrefix(assignment.operator, valueVmDt, null, symbol)
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"+=" -> expressionEval.operatorPlusInplace(null, symbol, targetDt, value)
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"-=" -> expressionEval.operatorMinusInplace(null, symbol, targetDt, value)
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"*=" -> expressionEval.operatorMultiplyInplace(null, symbol, targetDt, value)
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"/=" -> expressionEval.operatorDivideInplace(null, symbol, targetDt, value.type in SignedDatatypes, value)
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"|=" -> expressionEval.operatorOrInplace(null, symbol, targetDt, value)
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"&=" -> expressionEval.operatorAndInplace(null, symbol, targetDt, value)
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"^=" -> expressionEval.operatorXorInplace(null, symbol, targetDt, value)
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"<<=" -> expressionEval.operatorShiftLeftInplace(null, symbol, targetDt, value)
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">>=" -> expressionEval.operatorShiftRightInplace(null, symbol, targetDt, value.type in SignedDatatypes, value)
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"%=" -> expressionEval.operatorModuloInplace(null, symbol, targetDt, value)
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"==" -> expressionEval.operatorEqualsInplace(null, symbol, targetDt, value)
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"!=" -> expressionEval.operatorNotEqualsInplace(null, symbol, targetDt, value)
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"<" -> expressionEval.operatorLessInplace(null, symbol, targetDt, value.type in SignedDatatypes, value)
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">" -> expressionEval.operatorGreaterInplace(null, symbol, targetDt, value.type in SignedDatatypes, value)
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"<=" -> expressionEval.operatorLessEqualInplace(null, symbol, targetDt, value.type in SignedDatatypes, value)
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">=" -> expressionEval.operatorGreaterEqualInplace(null, symbol, targetDt, value.type in SignedDatatypes, value)
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in PrefixOperators -> inplacePrefix(assignment.operator, targetDt, null, symbol)
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else -> throw AssemblyError("invalid augmented assign operator ${assignment.operator}")
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}
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}
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@ -268,7 +268,9 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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actualResultReg2 = tr.resultReg
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addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2), null)
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}
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DataType.WORD -> { }
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DataType.WORD -> {
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actualResultReg2 = tr.resultReg
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}
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DataType.FLOAT -> {
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actualResultReg2 = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.FTOUW, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null)
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@ -288,7 +290,9 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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actualResultReg2 = tr.resultReg
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addInstr(result, IRInstruction(Opcode.EXT, type = IRDataType.BYTE, reg1 = actualResultReg2), null)
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}
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DataType.UWORD -> { }
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DataType.UWORD -> {
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actualResultReg2 = tr.resultReg
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}
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DataType.FLOAT -> {
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actualResultReg2 = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.FTOSW, IRDataType.FLOAT, reg1=actualResultReg2, fpReg1 = tr.resultFpReg), null)
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@ -316,6 +320,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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else -> throw AssemblyError("weird cast type")
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}
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return ExpressionCodeResult(result, codeGen.irType(cast.type), actualResultReg2, actualResultFpReg2)
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}
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@ -556,17 +561,17 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val rightTr = translateExpression(binExpr.right)
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addToResult(result, rightTr, -1, rightTr.resultFpReg)
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val resultRegister = codeGen.registers.nextFree()
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val valueReg = codeGen.registers.nextFree()
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val label = codeGen.createLabelName()
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, value=1), null)
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addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=valueReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
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if (notEquals) {
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addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
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addInstr(result, IRInstruction(Opcode.BNZ, IRDataType.BYTE, reg1=valueReg, labelSymbol = label), null)
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} else {
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val label = codeGen.createLabelName()
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val valueReg = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, value=1), null)
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addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=valueReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null)
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addInstr(result, IRInstruction(Opcode.BZ, IRDataType.BYTE, reg1=valueReg, labelSymbol = label), null)
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, value=0), null)
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result += IRCodeChunk(label, null)
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}
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addInstr(result, IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=resultRegister, value=0), null)
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result += IRCodeChunk(label, null)
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return ExpressionCodeResult(result, IRDataType.BYTE, resultRegister, -1)
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} else {
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if(binExpr.left.type==DataType.STR && binExpr.right.type==DataType.STR) {
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@ -1208,152 +1213,124 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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}
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fun operatorEqualsInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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if(knownAddress!=null) {
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// @(address) = @(address) == operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(Opcode.SEQ, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
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}
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return if(vmDt==IRDataType.FLOAT) {
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createInplaceFloatComparison(knownAddress, symbol, operand, Opcode.SEQ)
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} else {
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// symbol = symbol == operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
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it += IRInstruction(Opcode.SEQ, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
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}
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createInplaceComparison(knownAddress, symbol, vmDt, operand, Opcode.SEQ)
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}
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return result
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}
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fun operatorNotEqualsInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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if(knownAddress!=null) {
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// @(address) = @(address) != operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(Opcode.SNE, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
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}
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return if(vmDt==IRDataType.FLOAT) {
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createInplaceFloatComparison(knownAddress, symbol, operand, Opcode.SNE)
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} else {
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// symbol = symbol != operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
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it += IRInstruction(Opcode.SNE, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
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}
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createInplaceComparison(knownAddress, symbol, vmDt, operand, Opcode.SNE)
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}
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return result
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}
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fun operatorGreaterInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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val opcode = if(signed) Opcode.SGTS else Opcode.SGT
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if(knownAddress!=null) {
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// @(address) = @(address) > operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
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}
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return if(vmDt==IRDataType.FLOAT) {
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createInplaceFloatComparison(knownAddress, symbol, operand, opcode)
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} else {
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// symbol = symbol > operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
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it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
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}
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createInplaceComparison(knownAddress, symbol, vmDt, operand, opcode)
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}
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return result
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}
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fun operatorLessInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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val opcode = if(signed) Opcode.SLTS else Opcode.SLT
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if(knownAddress!=null) {
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// @(address) = @(address) < operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
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}
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return if(vmDt==IRDataType.FLOAT) {
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createInplaceFloatComparison(knownAddress, symbol, operand, opcode)
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} else {
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// symbol = symbol < operand
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
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it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
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}
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createInplaceComparison(knownAddress, symbol, vmDt, operand, opcode)
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}
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return result
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}
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fun operatorGreaterEqualInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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val opcode = if(signed) Opcode.SGES else Opcode.SGE
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if(knownAddress!=null) {
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// @(address) = @(address) > operand
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return if(vmDt==IRDataType.FLOAT) {
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createInplaceFloatComparison(knownAddress, symbol, operand, opcode)
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} else {
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createInplaceComparison(knownAddress, symbol, vmDt, operand, opcode)
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}
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}
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fun operatorLessEqualInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
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val opcode = if(signed) Opcode.SLES else Opcode.SLE
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return if(vmDt==IRDataType.FLOAT) {
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createInplaceFloatComparison(knownAddress, symbol, operand, opcode)
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} else {
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createInplaceComparison(knownAddress, symbol, vmDt, operand, opcode)
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}
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}
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private fun createInplaceComparison(
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knownAddress: Int?,
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symbol: String?,
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vmDt: IRDataType,
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operand: PtExpression,
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compareAndSetOpcode: Opcode
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): MutableList<IRCodeChunkBase> {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand) // TODO optimize if operand is PtNumber?
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addToResult(result, tr, tr.resultReg, -1)
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if (knownAddress != null) {
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// in-place modify a memory location
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(Opcode.LOADM, vmDt, reg1 = valueReg, value = knownAddress)
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it += IRInstruction(compareAndSetOpcode, vmDt, reg1 = valueReg, reg2 = tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1 = valueReg, value = knownAddress)
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}
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} else {
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// symbol = symbol > operand
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// in-place modify a symbol (variable)
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val valueReg = codeGen.registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
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it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
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it += IRInstruction(Opcode.LOADM, vmDt, reg1 = valueReg, labelSymbol = symbol)
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it += IRInstruction(compareAndSetOpcode, vmDt, reg1 = valueReg, reg2 = tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1 = valueReg, labelSymbol = symbol)
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}
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}
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return result
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}
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fun operatorLessEqualInplace(knownAddress: Int?, symbol: String?, vmDt: IRDataType, signed: Boolean, operand: PtExpression): IRCodeChunks {
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private fun createInplaceFloatComparison(
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knownAddress: Int?,
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symbol: String?,
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operand: PtExpression,
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compareAndSetOpcode: Opcode
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): MutableList<IRCodeChunkBase> {
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val result = mutableListOf<IRCodeChunkBase>()
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val tr = translateExpression(operand)
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addToResult(result, tr, tr.resultReg, -1)
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val opcode = if(signed) Opcode.SLES else Opcode.SLE
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if(knownAddress!=null) {
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// @(address) = @(address) > operand
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val valueReg = codeGen.registers.nextFree()
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val tr = translateExpression(operand) // TODO optimize if operand is PtNumber?
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addToResult(result, tr, -1, tr.resultFpReg)
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val valueReg = codeGen.registers.nextFreeFloat()
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val cmpReg = codeGen.registers.nextFree()
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val zeroReg = codeGen.registers.nextFree()
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if (knownAddress != null) {
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// in-place modify a memory location
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, value=knownAddress)
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it += IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1 = valueReg, value = knownAddress)
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it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=cmpReg, fpReg1 = valueReg, fpReg2 = tr.resultFpReg)
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroReg, value=0)
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it += IRInstruction(compareAndSetOpcode, IRDataType.BYTE, reg1=cmpReg, reg2=zeroReg)
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it += IRInstruction(Opcode.FFROMUB, IRDataType.FLOAT, reg1=cmpReg, fpReg1 = valueReg)
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it += IRInstruction(Opcode.STOREM, IRDataType.FLOAT, fpReg1 = valueReg, value=knownAddress)
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}
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} else {
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// symbol = symbol > operand
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val valueReg = codeGen.registers.nextFree()
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// in-place modify a symbol (variable)
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, vmDt, reg1=valueReg, labelSymbol = symbol)
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it += IRInstruction(opcode, vmDt, reg1=valueReg, reg2=tr.resultReg)
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it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueReg, labelSymbol = symbol)
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it += IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1 = valueReg, labelSymbol = symbol)
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it += IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=cmpReg, fpReg1 = valueReg, fpReg2 = tr.resultFpReg)
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=zeroReg, value=0)
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it += IRInstruction(compareAndSetOpcode, IRDataType.BYTE, reg1=cmpReg, reg2=zeroReg)
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it += IRInstruction(Opcode.FFROMUB, IRDataType.FLOAT, reg1=cmpReg, fpReg1 = valueReg)
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it += IRInstruction(Opcode.STOREM, IRDataType.FLOAT, fpReg1 = valueReg, labelSymbol = symbol)
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}
|
||||
}
|
||||
return result
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -4,11 +4,9 @@ TODO
|
||||
|
||||
For next minor release
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
newxpr vm: vm/bsieve.p8 has wrong result
|
||||
once everything works, disable -newexpr option for IR/virtual target because that already works without eval stack
|
||||
disable -newexpr option for IR/virtual target because that already works without eval stack
|
||||
and creates far superior code without the newexpr flattening.
|
||||
|
||||
IR (normal): fix reg1 out of bounds crash in compiler/test/comparisons/test_compares.p8
|
||||
-> move the transform to the 6502 codegen again ? instead of doing it in compiler itself?
|
||||
|
||||
...
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user