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IR: use INV instead of XOR for bitwise invert
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parent
64c132ee0a
commit
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@ -126,21 +126,8 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val code= IRCodeChunk(null, null)
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when(operator) {
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"+" -> { }
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"-" -> {
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code += if(address!=null)
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IRInstruction(Opcode.NEGM, vmDt, address = address)
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else
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IRInstruction(Opcode.NEGM, vmDt, labelSymbol = symbol)
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}
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"~" -> {
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val regMask = codeGen.registers.nextFree()
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val mask = if(vmDt==IRDataType.BYTE) 0x00ff else 0xffff
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code += IRInstruction(Opcode.LOAD, vmDt, reg1=regMask, immediate = mask)
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code += if(address!=null)
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IRInstruction(Opcode.XORM, vmDt, reg1=regMask, address = address)
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else
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IRInstruction(Opcode.XORM, vmDt, reg1=regMask, labelSymbol = symbol)
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}
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"-" -> code += IRInstruction(Opcode.NEGM, vmDt, address = address, labelSymbol = symbol)
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"~" -> code += IRInstruction(Opcode.INVM, vmDt, address = address, labelSymbol = symbol)
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else -> throw AssemblyError("weird prefix operator")
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}
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return listOf(code)
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@ -259,8 +259,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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addInstr(result, IRInstruction(Opcode.NEG, vmDt, reg1 = tr.resultReg), null)
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}
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"~" -> {
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val mask = if(vmDt==IRDataType.BYTE) 0x00ff else 0xffff
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addInstr(result, IRInstruction(Opcode.XOR, vmDt, reg1 = tr.resultReg, immediate = mask), null)
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addInstr(result, IRInstruction(Opcode.INV, vmDt, reg1 = tr.resultReg), null)
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}
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else -> throw AssemblyError("weird prefix operator")
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}
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