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https://github.com/irmen/prog8.git
synced 2026-04-20 11:17:01 +00:00
IR: fix problems with symbol offsets and unused subroutines/chunks
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@@ -229,11 +229,11 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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if(fixedIndex!=null) {
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val chunk = IRCodeChunk(null, null).also {
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if(targetArray.splitWords) {
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it += IRInstruction(Opcode.STOREZM, IRDataType.BYTE, immediate = arrayLength, labelSymbol = "${variable}_lsb+$fixedIndex")
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it += IRInstruction(Opcode.STOREZM, IRDataType.BYTE, immediate = arrayLength, labelSymbol = "${variable}_msb+$fixedIndex")
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it += IRInstruction(Opcode.STOREZM, IRDataType.BYTE, immediate = arrayLength, labelSymbol = "${variable}_lsb", symbolOffset = fixedIndex)
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it += IRInstruction(Opcode.STOREZM, IRDataType.BYTE, immediate = arrayLength, labelSymbol = "${variable}_msb", symbolOffset = fixedIndex)
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}
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else
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it += IRInstruction(Opcode.STOREZM, targetDt, labelSymbol = "$variable+${fixedIndex*itemsize}")
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it += IRInstruction(Opcode.STOREZM, targetDt, labelSymbol = variable, symbolOffset = fixedIndex*itemsize)
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}
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result += chunk
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} else {
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@@ -253,7 +253,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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val chunk = IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREM, targetDt, fpReg1 = valueFpRegister, labelSymbol = "$variable+$offset")
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it += IRInstruction(Opcode.STOREM, targetDt, fpReg1 = valueFpRegister, labelSymbol = variable, symbolOffset = offset)
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}
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result += chunk
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} else {
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@@ -268,12 +268,12 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val chunk = IRCodeChunk(null, null).also {
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if(targetArray.splitWords) {
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val msbReg = codeGen.registers.nextFree()
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueRegister, immediate = arrayLength, labelSymbol = "${variable}_lsb+$fixedIndex")
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = valueRegister, immediate = arrayLength, labelSymbol = "${variable}_lsb", symbolOffset = fixedIndex)
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it += IRInstruction(Opcode.MSIG, IRDataType.BYTE, reg1 = msbReg, reg2 = valueRegister)
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = msbReg, immediate = arrayLength, labelSymbol = "${variable}_msb+$fixedIndex")
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it += IRInstruction(Opcode.STOREM, IRDataType.BYTE, reg1 = msbReg, immediate = arrayLength, labelSymbol = "${variable}_msb", symbolOffset = fixedIndex)
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}
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else
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it += IRInstruction(Opcode.STOREM, targetDt, reg1 = valueRegister, labelSymbol = "$variable+${fixedIndex*itemsize}")
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it += IRInstruction(Opcode.STOREM, targetDt, reg1 = valueRegister, labelSymbol = variable, symbolOffset = fixedIndex*itemsize)
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}
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result += chunk
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} else {
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@@ -188,8 +188,8 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val memOffset = (arrayIx.index as PtNumber).number.toInt()
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result += IRCodeChunk(null, null).also {
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val tmpRegMsb = codeGen.registers.nextFree()
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it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=tmpRegMsb, immediate = arrayLength, labelSymbol= "${arrayVarSymbol}_msb+$memOffset")
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it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=resultRegister, immediate = arrayLength, labelSymbol= "${arrayVarSymbol}_lsb+$memOffset")
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it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=tmpRegMsb, immediate = arrayLength, labelSymbol= "${arrayVarSymbol}_msb", symbolOffset = memOffset)
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it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=resultRegister, immediate = arrayLength, labelSymbol= "${arrayVarSymbol}_lsb", symbolOffset = memOffset)
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it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1=finalResultReg, reg2=tmpRegMsb, reg3=resultRegister)
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}
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} else {
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@@ -207,14 +207,14 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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var resultFpRegister = -1
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if(arrayIx.index is PtNumber) {
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val memOffset = ((arrayIx.index as PtNumber).number.toInt() * eltSize).toString()
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val memOffset = ((arrayIx.index as PtNumber).number.toInt() * eltSize)
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if(vmDt==IRDataType.FLOAT) {
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resultFpRegister = codeGen.registers.nextFreeFloat()
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addInstr(result, IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1=resultFpRegister, labelSymbol = "$arrayVarSymbol+$memOffset"), null)
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addInstr(result, IRInstruction(Opcode.LOADM, IRDataType.FLOAT, fpReg1=resultFpRegister, labelSymbol = arrayVarSymbol, symbolOffset = memOffset), null)
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}
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else {
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resultRegister = codeGen.registers.nextFree()
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addInstr(result, IRInstruction(Opcode.LOADM, vmDt, reg1=resultRegister, labelSymbol = "$arrayVarSymbol+$memOffset"), null)
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addInstr(result, IRInstruction(Opcode.LOADM, vmDt, reg1=resultRegister, labelSymbol = arrayVarSymbol, symbolOffset = memOffset), null)
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}
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} else {
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val tr = translateExpression(arrayIx.index)
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@@ -143,19 +143,10 @@ class IRCodeGen(
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(idx, instr) ->
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val symbolExpr = instr.labelSymbol
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if(symbolExpr!=null) {
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val symbol: String
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val index: UInt
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if('+' in symbolExpr) {
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val operands = symbolExpr.split('+', )
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symbol = operands[0]
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index = operands[1].toUInt()
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} else {
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symbol = symbolExpr
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index = 0u
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}
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val target = symbolTable.flat[symbol]
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val index = instr.labelSymbolOffset ?: 0
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val target = symbolTable.flat[symbolExpr]
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if (target is StMemVar) {
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replacements.add(Triple(chunk, idx, target.address+index))
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replacements.add(Triple(chunk, idx, target.address+index.toUInt()))
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}
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}
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}
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@@ -1451,21 +1442,21 @@ class IRCodeGen(
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when(postIncrDecr.operator) {
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"++" -> {
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.INCM, IRDataType.BYTE, labelSymbol = "${variable}_lsb+$fixedIndex")
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it += IRInstruction(Opcode.INCM, IRDataType.BYTE, labelSymbol = "${variable}_lsb", symbolOffset = fixedIndex)
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it += IRInstruction(Opcode.BSTNE, labelSymbol = skipLabel)
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it += IRInstruction(Opcode.INCM, IRDataType.BYTE, labelSymbol = "${variable}_msb+$fixedIndex")
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it += IRInstruction(Opcode.INCM, IRDataType.BYTE, labelSymbol = "${variable}_msb", symbolOffset = fixedIndex)
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}
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result += IRCodeChunk(skipLabel, null)
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}
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"--" -> {
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val valueReg=registers.nextFree()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=valueReg, labelSymbol = "${variable}_lsb+$fixedIndex")
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it += IRInstruction(Opcode.LOADM, IRDataType.BYTE, reg1=valueReg, labelSymbol = "${variable}_lsb", symbolOffset = fixedIndex)
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it += IRInstruction(Opcode.BSTNE, labelSymbol = skipLabel)
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it += IRInstruction(Opcode.DECM, IRDataType.BYTE, labelSymbol = "${variable}_msb+$fixedIndex")
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it += IRInstruction(Opcode.DECM, IRDataType.BYTE, labelSymbol = "${variable}_msb", symbolOffset = fixedIndex)
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}
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result += IRCodeChunk(skipLabel, null).also {
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it += IRInstruction(Opcode.DECM, IRDataType.BYTE, labelSymbol = "${variable}_lsb+$fixedIndex")
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it += IRInstruction(Opcode.DECM, IRDataType.BYTE, labelSymbol = "${variable}_lsb", symbolOffset = fixedIndex)
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}
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}
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else -> throw AssemblyError("weird operator")
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@@ -1556,7 +1547,7 @@ class IRCodeGen(
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it += IRInstruction(Opcode.STOREIX, irDt, reg1 = dataReg, reg2 = indexReg, labelSymbol = variable)
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}
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} else {
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addInstr(result, IRInstruction(operationMem, irDt, labelSymbol = "$variable+$offset"), null)
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addInstr(result, IRInstruction(operationMem, irDt, labelSymbol = variable, symbolOffset = offset), null)
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}
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} else {
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val indexTr = expressionEval.translateExpression(array.index)
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@@ -167,7 +167,13 @@ class IRUnusedCodeRemover(
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it.next?.let { next -> new += next }
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it.instructions.forEach { instr ->
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if (instr.branchTarget == null)
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instr.labelSymbol?.let { label -> allLabeledChunks[label]?.let { chunk -> new += chunk } }
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instr.labelSymbol?.let { label ->
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val chunk = allLabeledChunks[label.substringBeforeLast('.')]
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if(chunk!=null)
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new+=chunk
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else
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allLabeledChunks[label]?.let { new += it }
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}
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else
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new += instr.branchTarget!!
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}
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@@ -214,6 +220,16 @@ class IRUnusedCodeRemover(
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linkedChunks += chunk
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}
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// make sure that chunks that are only used as a prefix of a label, are also marked as linked
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linkedChunks.forEach { chunk ->
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chunk.instructions.forEach {
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if(it.labelSymbol!=null) {
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val chunkName = it.labelSymbol!!.substringBeforeLast('.')
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allLabeledChunks[chunkName]?.let { linkedChunks+=it }
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}
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}
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}
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return removeUnlinkedChunks(linkedChunks)
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}
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