mirror of
https://github.com/irmen/prog8.git
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cleanup double code
This commit is contained in:
Irmen de Jong
parent
402827497e
commit
9735527062
@ -14,6 +14,10 @@ import prog8.compiler.target.c64.C64MachineDefinition.ESTACK_HI_HEX
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import prog8.compiler.target.c64.C64MachineDefinition.ESTACK_LO_HEX
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import prog8.compiler.toHex
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// OLD inplace-assignment code.
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// should really come up with a more compact way to generate this kind of code...
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/***
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internal class InplaceAssignmentAsmGen(private val program: Program, private val errors: ErrorReporter, private val asmgen: AsmGen) {
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@ -734,657 +738,7 @@ internal class InplaceAssignmentAsmGen(private val program: Program, private val
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}
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}
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}
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// old code-generation below:
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// eventually, all of this should have been replaced by newer more optimized code above.
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private fun translateNormalAssignment(assign: Assignment) {
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when (assign.value) {
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is NumericLiteralValue -> {
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val numVal = assign.value as NumericLiteralValue
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when (numVal.type) {
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DataType.UBYTE, DataType.BYTE -> assignFromByteConstant(assign.target, numVal.number.toShort())
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DataType.UWORD, DataType.WORD -> assignFromWordConstant(assign.target, numVal.number.toInt())
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DataType.FLOAT -> assignFromFloatConstant(assign.target, numVal.number.toDouble())
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else -> throw AssemblyError("weird numval type")
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}
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}
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is IdentifierReference -> {
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when (val type = assign.target.inferType(program, assign).typeOrElse(DataType.STRUCT)) {
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DataType.UBYTE, DataType.BYTE -> assignFromByteVariable(assign.target, assign.value as IdentifierReference)
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DataType.UWORD, DataType.WORD -> assignFromWordVariable(assign.target, assign.value as IdentifierReference)
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DataType.FLOAT -> assignFromFloatVariable(assign.target, assign.value as IdentifierReference)
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else -> throw AssemblyError("unsupported assignment target type $type")
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}
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}
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is AddressOf -> {
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val identifier = (assign.value as AddressOf).identifier
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assignFromAddressOf(assign.target, identifier)
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}
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is DirectMemoryRead -> {
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val read = (assign.value as DirectMemoryRead)
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when (read.addressExpression) {
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is NumericLiteralValue -> {
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val address = (read.addressExpression as NumericLiteralValue).number.toInt()
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assignFromMemoryByte(assign.target, address, null)
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}
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is IdentifierReference -> {
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assignFromMemoryByte(assign.target, null, read.addressExpression as IdentifierReference)
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}
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else -> {
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throw AssemblyError("missing asm gen for memread assignment into ${assign.target}")
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}
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}
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}
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is PrefixExpression -> {
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// TODO optimize common cases
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asmgen.translateExpression(assign.value as PrefixExpression)
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assignFromEvalResult(assign.target)
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}
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is BinaryExpression -> {
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// TODO optimize common cases
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asmgen.translateExpression(assign.value as BinaryExpression)
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assignFromEvalResult(assign.target)
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}
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is ArrayIndexedExpression -> {
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// TODO optimize common cases
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val arrayExpr = assign.value as ArrayIndexedExpression
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val arrayDt = arrayExpr.identifier.inferType(program).typeOrElse(DataType.STRUCT)
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val index = arrayExpr.arrayspec.index
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if (index is NumericLiteralValue) {
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// constant array index value
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val arrayVarName = asmgen.asmIdentifierName(arrayExpr.identifier)
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val indexValue = index.number.toInt() * ArrayElementTypes.getValue(arrayDt).memorySize()
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when (arrayDt) {
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DataType.STR, DataType.ARRAY_UB, DataType.ARRAY_B ->
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asmgen.out(" lda $arrayVarName+$indexValue | sta $ESTACK_LO_HEX,x | dex")
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DataType.ARRAY_UW, DataType.ARRAY_W ->
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asmgen.out(" lda $arrayVarName+$indexValue | sta $ESTACK_LO_HEX,x | lda $arrayVarName+$indexValue+1 | sta $ESTACK_HI_HEX,x | dex")
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DataType.ARRAY_F ->
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asmgen.out(" lda #<$arrayVarName+$indexValue | ldy #>$arrayVarName+$indexValue | jsr c64flt.push_float")
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else ->
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throw AssemblyError("weird array type")
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}
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} else {
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asmgen.translateArrayIndexIntoA(arrayExpr)
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asmgen.readAndPushArrayvalueWithIndexA(arrayDt, arrayExpr.identifier)
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}
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assignFromEvalResult(assign.target)
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}
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is TypecastExpression -> {
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val cast = assign.value as TypecastExpression
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val sourceType = cast.expression.inferType(program)
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val targetType = assign.target.inferType(program, assign)
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if (sourceType.isKnown && targetType.isKnown &&
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(sourceType.typeOrElse(DataType.STRUCT) in ByteDatatypes && targetType.typeOrElse(DataType.STRUCT) in ByteDatatypes) ||
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(sourceType.typeOrElse(DataType.STRUCT) in WordDatatypes && targetType.typeOrElse(DataType.STRUCT) in WordDatatypes)) {
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// no need for a type cast
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assign.value = cast.expression
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translate(assign)
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} else {
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asmgen.translateExpression(assign.value as TypecastExpression)
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assignFromEvalResult(assign.target)
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}
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}
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is FunctionCall -> {
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asmgen.translateExpression(assign.value as FunctionCall)
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assignFromEvalResult(assign.target)
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}
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is ArrayLiteralValue, is StringLiteralValue -> throw AssemblyError("no asm gen for string/array assignment $assign")
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is RangeExpr -> throw AssemblyError("range expression should have been changed into array values ${assign.value.position}")
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}
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}
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internal fun assignFromEvalResult(target: AssignTarget) {
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val targetIdent = target.identifier
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when {
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targetIdent != null -> {
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val targetName = asmgen.asmIdentifierName(targetIdent)
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when (val targetDt = targetIdent.inferType(program).typeOrElse(DataType.STRUCT)) {
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DataType.UBYTE, DataType.BYTE -> {
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asmgen.out(" inx | lda $ESTACK_LO_HEX,x | sta $targetName")
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}
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DataType.UWORD, DataType.WORD -> {
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asmgen.out("""
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inx
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lda $ESTACK_LO_HEX,x
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sta $targetName
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lda $ESTACK_HI_HEX,x
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sta $targetName+1
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""")
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}
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DataType.FLOAT -> {
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asmgen.out("""
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lda #<$targetName
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ldy #>$targetName
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jsr c64flt.pop_float
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""")
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}
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else -> throw AssemblyError("weird target variable type $targetDt")
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}
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}
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target.memoryAddress != null -> {
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asmgen.out(" inx | ldy $ESTACK_LO_HEX,x")
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storeRegisterInMemoryAddress(CpuRegister.Y, target.memoryAddress)
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}
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target.arrayindexed != null -> {
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val arrayDt = target.arrayindexed!!.identifier.inferType(program).typeOrElse(DataType.STRUCT)
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val arrayVarName = asmgen.asmIdentifierName(target.arrayindexed!!.identifier)
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asmgen.translateExpression(target.arrayindexed!!.arrayspec.index)
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asmgen.out(" inx | lda $ESTACK_LO_HEX,x")
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popAndWriteArrayvalueWithIndexA(arrayDt, arrayVarName)
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}
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else -> throw AssemblyError("weird assignment target $target")
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}
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}
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internal fun assignFromAddressOf(target: AssignTarget, name: IdentifierReference) {
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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val struct = name.memberOfStruct(program.namespace)
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val sourceName = if (struct != null) {
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// take the address of the first struct member instead
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val decl = name.targetVarDecl(program.namespace)!!
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val firstStructMember = struct.nameOfFirstMember()
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// find the flattened var that belongs to this first struct member
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val firstVarName = listOf(decl.name, firstStructMember)
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val firstVar = name.definingScope().lookup(firstVarName, name) as VarDecl
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firstVar.name
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} else {
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asmgen.fixNameSymbols(name.nameInSource.joinToString("."))
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}
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when {
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targetIdent != null -> {
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val targetName = asmgen.asmIdentifierName(targetIdent)
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asmgen.out("""
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lda #<$sourceName
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ldy #>$sourceName
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sta $targetName
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sty $targetName+1
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""")
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}
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target.memoryAddress != null -> {
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throw AssemblyError("no asm gen for assign address $sourceName to memory word $target")
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}
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targetArrayIdx != null -> {
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val index = targetArrayIdx.arrayspec.index
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val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
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throw AssemblyError("no asm gen for assign address $sourceName to array $targetName [ $index ]")
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}
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else -> throw AssemblyError("no asm gen for assign address $sourceName to $target")
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}
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}
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internal fun assignFromWordVariable(target: AssignTarget, variable: IdentifierReference) {
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val sourceName = asmgen.asmIdentifierName(variable)
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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when {
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targetIdent != null -> {
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val targetName = asmgen.asmIdentifierName(targetIdent)
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asmgen.out("""
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lda $sourceName
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ldy $sourceName+1
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sta $targetName
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sty $targetName+1
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""")
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}
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target.memoryAddress != null -> {
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throw AssemblyError("no asm gen for assign wordvar $sourceName to memory ${target.memoryAddress}")
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}
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targetArrayIdx != null -> {
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val index = targetArrayIdx.arrayspec.index
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val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
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asmgen.out(" lda $sourceName | sta $ESTACK_LO_HEX,x | lda $sourceName+1 | sta $ESTACK_HI_HEX,x | dex")
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asmgen.translateExpression(index)
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asmgen.out(" inx | lda $ESTACK_LO_HEX,x")
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val arrayDt = targetArrayIdx.identifier.inferType(program).typeOrElse(DataType.STRUCT)
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popAndWriteArrayvalueWithIndexA(arrayDt, targetName)
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}
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else -> throw AssemblyError("no asm gen for assign wordvar to $target")
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}
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}
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internal fun assignFromFloatVariable(target: AssignTarget, variable: IdentifierReference) {
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val sourceName = asmgen.asmIdentifierName(variable)
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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when {
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targetIdent != null -> {
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val targetName = asmgen.asmIdentifierName(targetIdent)
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asmgen.out("""
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lda $sourceName
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sta $targetName
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lda $sourceName+1
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sta $targetName+1
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lda $sourceName+2
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sta $targetName+2
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lda $sourceName+3
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sta $targetName+3
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lda $sourceName+4
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sta $targetName+4
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""")
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}
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targetArrayIdx != null -> {
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val index = targetArrayIdx.arrayspec.index
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val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
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asmgen.out(" lda #<$sourceName | ldy #>$sourceName | jsr c64flt.push_float")
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asmgen.translateExpression(index)
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asmgen.out(" lda #<$targetName | ldy #>$targetName | jsr c64flt.pop_float_to_indexed_var")
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}
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else -> throw AssemblyError("no asm gen for assign floatvar to $target")
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}
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}
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internal fun assignFromByteVariable(target: AssignTarget, variable: IdentifierReference) {
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val sourceName = asmgen.asmIdentifierName(variable)
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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when {
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targetIdent != null -> {
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val targetName = asmgen.asmIdentifierName(targetIdent)
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asmgen.out("""
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lda $sourceName
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sta $targetName
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""")
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}
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targetArrayIdx != null -> {
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val index = targetArrayIdx.arrayspec.index
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val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
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val arrayDt = targetArrayIdx.identifier.inferType(program).typeOrElse(DataType.STRUCT)
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asmgen.out(" lda $sourceName | sta $ESTACK_LO_HEX,x | dex")
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asmgen.translateExpression(index)
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asmgen.out(" inx | lda $ESTACK_LO_HEX,x")
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popAndWriteArrayvalueWithIndexA(arrayDt, targetName)
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}
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target.memoryAddress != null -> {
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val addressExpr = target.memoryAddress.addressExpression
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val addressLv = addressExpr as? NumericLiteralValue
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when {
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addressLv != null -> asmgen.out(" lda $sourceName | sta ${addressLv.number.toHex()}")
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addressExpr is IdentifierReference -> {
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val targetName = asmgen.asmIdentifierName(addressExpr)
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asmgen.out(" lda $sourceName | sta $targetName")
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}
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else -> {
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asmgen.translateExpression(addressExpr)
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asmgen.out("""
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inx
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lda $ESTACK_LO_HEX,x
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ldy $ESTACK_HI_HEX,x
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sta (+) +1
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sty (+) +2
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lda $sourceName
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+ sta ${'$'}ffff ; modified
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""")
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}
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}
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}
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else -> throw AssemblyError("no asm gen for assign bytevar to $target")
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}
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}
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internal fun assignFromRegister(target: AssignTarget, register: CpuRegister) {
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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when {
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targetIdent != null -> {
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val targetName = asmgen.asmIdentifierName(targetIdent)
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asmgen.out(" st${register.name.toLowerCase()} $targetName")
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}
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target.memoryAddress != null -> {
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storeRegisterInMemoryAddress(register, target.memoryAddress)
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}
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targetArrayIdx != null -> {
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val index = targetArrayIdx.arrayspec.index
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val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
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when (index) {
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is NumericLiteralValue -> {
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val memindex = index.number.toInt()
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when (register) {
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CpuRegister.A -> asmgen.out(" sta $targetName+$memindex")
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CpuRegister.X -> asmgen.out(" stx $targetName+$memindex")
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CpuRegister.Y -> asmgen.out(" sty $targetName+$memindex")
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}
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}
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is IdentifierReference -> {
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when (register) {
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CpuRegister.A -> asmgen.out(" sta ${C64Zeropage.SCRATCH_B1}")
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CpuRegister.X -> asmgen.out(" stx ${C64Zeropage.SCRATCH_B1}")
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CpuRegister.Y -> asmgen.out(" sty ${C64Zeropage.SCRATCH_B1}")
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}
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asmgen.out("""
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lda ${asmgen.asmIdentifierName(index)}
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tay
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lda ${C64Zeropage.SCRATCH_B1}
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sta $targetName,y
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""")
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}
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else -> {
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asmgen.saveRegister(register)
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asmgen.translateExpression(index)
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asmgen.restoreRegister(register)
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when (register) {
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CpuRegister.A -> asmgen.out(" sta ${C64Zeropage.SCRATCH_B1}")
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CpuRegister.X -> asmgen.out(" stx ${C64Zeropage.SCRATCH_B1}")
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CpuRegister.Y -> asmgen.out(" sty ${C64Zeropage.SCRATCH_B1}")
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}
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asmgen.out("""
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inx
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lda $ESTACK_LO_HEX,x
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tay
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lda ${C64Zeropage.SCRATCH_B1}
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sta $targetName,y
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""")
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}
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}
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}
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else -> throw AssemblyError("no asm gen for assign register $register to $target")
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}
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}
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private fun storeRegisterInMemoryAddress(register: CpuRegister, memoryAddress: DirectMemoryWrite) {
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val addressExpr = memoryAddress.addressExpression
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val addressLv = addressExpr as? NumericLiteralValue
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val registerName = register.name.toLowerCase()
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when {
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addressLv != null -> asmgen.out(" st$registerName ${addressLv.number.toHex()}")
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addressExpr is IdentifierReference -> {
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val targetName = asmgen.asmIdentifierName(addressExpr)
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when (register) {
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CpuRegister.A -> asmgen.out("""
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ldy $targetName
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sty (+) +1
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ldy $targetName+1
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sty (+) +2
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+ sta ${'$'}ffff ; modified""")
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CpuRegister.X -> asmgen.out("""
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ldy $targetName
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sty (+) +1
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ldy $targetName+1
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sty (+) +2
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+ stx ${'$'}ffff ; modified""")
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CpuRegister.Y -> asmgen.out("""
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lda $targetName
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sta (+) +1
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lda $targetName+1
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sta (+) +2
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+ sty ${'$'}ffff ; modified""")
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}
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}
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else -> {
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asmgen.saveRegister(register)
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asmgen.translateExpression(addressExpr)
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asmgen.restoreRegister(register)
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when (register) {
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CpuRegister.A -> asmgen.out(" tay")
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CpuRegister.X -> throw AssemblyError("can't use X register here")
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CpuRegister.Y -> {}
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}
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asmgen.out("""
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inx
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lda $ESTACK_LO_HEX,x
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sta (+) +1
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lda $ESTACK_HI_HEX,x
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sta (+) +2
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+ sty ${'$'}ffff ; modified
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""")
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}
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}
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}
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internal fun assignFromWordConstant(target: AssignTarget, word: Int) {
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val targetIdent = target.identifier
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val targetArrayIdx = target.arrayindexed
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when {
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targetIdent != null -> {
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val targetName = asmgen.asmIdentifierName(targetIdent)
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if (word ushr 8 == word and 255) {
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// lsb=msb
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asmgen.out("""
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lda #${(word and 255).toHex()}
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sta $targetName
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sta $targetName+1
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""")
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} else {
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asmgen.out("""
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lda #<${word.toHex()}
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ldy #>${word.toHex()}
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sta $targetName
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sty $targetName+1
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""")
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}
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}
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target.memoryAddress != null -> {
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throw AssemblyError("no asm gen for assign word $word to memory ${target.memoryAddress}")
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}
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targetArrayIdx != null -> {
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val index = targetArrayIdx.arrayspec.index
|
||||
val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
|
||||
// TODO optimize common cases
|
||||
asmgen.translateExpression(index)
|
||||
asmgen.out("""
|
||||
inx
|
||||
lda $ESTACK_LO_HEX,x
|
||||
asl a
|
||||
tay
|
||||
lda #<${word.toHex()}
|
||||
sta $targetName,y
|
||||
lda #>${word.toHex()}
|
||||
sta $targetName+1,y
|
||||
""")
|
||||
}
|
||||
else -> throw AssemblyError("no asm gen for assign word $word to $target")
|
||||
}
|
||||
}
|
||||
|
||||
internal fun assignFromByteConstant(target: AssignTarget, byte: Short) {
|
||||
val targetIdent = target.identifier
|
||||
val targetArrayIdx = target.arrayindexed
|
||||
when {
|
||||
targetIdent != null -> {
|
||||
val targetName = asmgen.asmIdentifierName(targetIdent)
|
||||
asmgen.out(" lda #${byte.toHex()} | sta $targetName ")
|
||||
}
|
||||
target.memoryAddress != null -> {
|
||||
asmgen.out(" ldy #${byte.toHex()}")
|
||||
storeRegisterInMemoryAddress(CpuRegister.Y, target.memoryAddress)
|
||||
}
|
||||
targetArrayIdx != null -> {
|
||||
val index = targetArrayIdx.arrayspec.index
|
||||
val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
|
||||
// TODO optimize common cases
|
||||
asmgen.translateExpression(index)
|
||||
asmgen.out("""
|
||||
inx
|
||||
ldy $ESTACK_LO_HEX,x
|
||||
lda #${byte.toHex()}
|
||||
sta $targetName,y
|
||||
""")
|
||||
}
|
||||
else -> throw AssemblyError("no asm gen for assign byte $byte to $target")
|
||||
}
|
||||
}
|
||||
|
||||
internal fun assignFromFloatConstant(target: AssignTarget, float: Double) {
|
||||
val targetIdent = target.identifier
|
||||
val targetArrayIdx = target.arrayindexed
|
||||
if (float == 0.0) {
|
||||
// optimized case for float zero
|
||||
when {
|
||||
targetIdent != null -> {
|
||||
val targetName = asmgen.asmIdentifierName(targetIdent)
|
||||
asmgen.out("""
|
||||
lda #0
|
||||
sta $targetName
|
||||
sta $targetName+1
|
||||
sta $targetName+2
|
||||
sta $targetName+3
|
||||
sta $targetName+4
|
||||
""")
|
||||
}
|
||||
targetArrayIdx != null -> {
|
||||
val index = targetArrayIdx.arrayspec.index
|
||||
val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
|
||||
if (index is NumericLiteralValue) {
|
||||
val indexValue = index.number.toInt() * C64MachineDefinition.FLOAT_MEM_SIZE
|
||||
asmgen.out("""
|
||||
lda #0
|
||||
sta $targetName+$indexValue
|
||||
sta $targetName+$indexValue+1
|
||||
sta $targetName+$indexValue+2
|
||||
sta $targetName+$indexValue+3
|
||||
sta $targetName+$indexValue+4
|
||||
""")
|
||||
} else {
|
||||
asmgen.translateExpression(index)
|
||||
asmgen.out("""
|
||||
lda #<${targetName}
|
||||
sta ${C64Zeropage.SCRATCH_W1}
|
||||
lda #>${targetName}
|
||||
sta ${C64Zeropage.SCRATCH_W1 + 1}
|
||||
jsr c64flt.set_0_array_float
|
||||
""")
|
||||
}
|
||||
}
|
||||
else -> throw AssemblyError("no asm gen for assign float 0.0 to $target")
|
||||
}
|
||||
} else {
|
||||
// non-zero value
|
||||
val constFloat = asmgen.getFloatConst(float)
|
||||
when {
|
||||
targetIdent != null -> {
|
||||
val targetName = asmgen.asmIdentifierName(targetIdent)
|
||||
asmgen.out("""
|
||||
lda $constFloat
|
||||
sta $targetName
|
||||
lda $constFloat+1
|
||||
sta $targetName+1
|
||||
lda $constFloat+2
|
||||
sta $targetName+2
|
||||
lda $constFloat+3
|
||||
sta $targetName+3
|
||||
lda $constFloat+4
|
||||
sta $targetName+4
|
||||
""")
|
||||
}
|
||||
targetArrayIdx != null -> {
|
||||
val index = targetArrayIdx.arrayspec.index
|
||||
val arrayVarName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
|
||||
if (index is NumericLiteralValue) {
|
||||
val indexValue = index.number.toInt() * C64MachineDefinition.FLOAT_MEM_SIZE
|
||||
asmgen.out("""
|
||||
lda $constFloat
|
||||
sta $arrayVarName+$indexValue
|
||||
lda $constFloat+1
|
||||
sta $arrayVarName+$indexValue+1
|
||||
lda $constFloat+2
|
||||
sta $arrayVarName+$indexValue+2
|
||||
lda $constFloat+3
|
||||
sta $arrayVarName+$indexValue+3
|
||||
lda $constFloat+4
|
||||
sta $arrayVarName+$indexValue+4
|
||||
""")
|
||||
} else {
|
||||
// TODO the index in A below seems to be clobbered?
|
||||
asmgen.translateArrayIndexIntoA(targetArrayIdx)
|
||||
asmgen.out("""
|
||||
lda #<${constFloat}
|
||||
sta ${C64Zeropage.SCRATCH_W1}
|
||||
lda #>${constFloat}
|
||||
sta ${C64Zeropage.SCRATCH_W1 + 1}
|
||||
lda #<${arrayVarName}
|
||||
sta ${C64Zeropage.SCRATCH_W2}
|
||||
lda #>${arrayVarName}
|
||||
sta ${C64Zeropage.SCRATCH_W2 + 1}
|
||||
jsr c64flt.set_array_float
|
||||
""")
|
||||
}
|
||||
}
|
||||
else -> throw AssemblyError("no asm gen for assign float $float to $target")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
internal fun assignFromMemoryByte(target: AssignTarget, address: Int?, identifier: IdentifierReference?) {
|
||||
val targetIdent = target.identifier
|
||||
val targetArrayIdx = target.arrayindexed
|
||||
if (address != null) {
|
||||
when {
|
||||
targetIdent != null -> {
|
||||
val targetName = asmgen.asmIdentifierName(targetIdent)
|
||||
asmgen.out("""
|
||||
lda ${address.toHex()}
|
||||
sta $targetName
|
||||
""")
|
||||
}
|
||||
target.memoryAddress != null -> {
|
||||
asmgen.out(" ldy ${address.toHex()}")
|
||||
storeRegisterInMemoryAddress(CpuRegister.Y, target.memoryAddress)
|
||||
}
|
||||
targetArrayIdx != null -> {
|
||||
val index = targetArrayIdx.arrayspec.index
|
||||
val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
|
||||
throw AssemblyError("no asm gen for assign memory byte at $address to array $targetName [ $index ]")
|
||||
}
|
||||
else -> throw AssemblyError("no asm gen for assign memory byte $target")
|
||||
}
|
||||
} else if (identifier != null) {
|
||||
val sourceName = asmgen.asmIdentifierName(identifier)
|
||||
when {
|
||||
targetIdent != null -> {
|
||||
val targetName = asmgen.asmIdentifierName(targetIdent)
|
||||
asmgen.out("""
|
||||
lda $sourceName
|
||||
sta (+) + 1
|
||||
lda $sourceName+1
|
||||
sta (+) + 2
|
||||
+ lda ${'$'}ffff\t; modified
|
||||
sta $targetName""")
|
||||
}
|
||||
target.memoryAddress != null -> {
|
||||
asmgen.out(" ldy $sourceName")
|
||||
storeRegisterInMemoryAddress(CpuRegister.Y, target.memoryAddress)
|
||||
}
|
||||
targetArrayIdx != null -> {
|
||||
val index = targetArrayIdx.arrayspec.index
|
||||
val targetName = asmgen.asmIdentifierName(targetArrayIdx.identifier)
|
||||
throw AssemblyError("no asm gen for assign memory byte $sourceName to array $targetName [ $index ]")
|
||||
}
|
||||
else -> throw AssemblyError("no asm gen for assign memory byte $target")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private fun popAndWriteArrayvalueWithIndexA(arrayDt: DataType, variablename: String) {
|
||||
when (arrayDt) {
|
||||
DataType.STR, DataType.ARRAY_UB, DataType.ARRAY_B ->
|
||||
asmgen.out(" tay | inx | lda $ESTACK_LO_HEX,x | sta $variablename,y")
|
||||
DataType.ARRAY_UW, DataType.ARRAY_W ->
|
||||
asmgen.out(" asl a | tay | inx | lda $ESTACK_LO_HEX,x | sta $variablename,y | lda $ESTACK_HI_HEX,x | sta $variablename+1,y")
|
||||
DataType.ARRAY_F ->
|
||||
// index * 5 is done in the subroutine that's called
|
||||
asmgen.out("""
|
||||
sta $ESTACK_LO_HEX,x
|
||||
dex
|
||||
lda #<$variablename
|
||||
ldy #>$variablename
|
||||
jsr c64flt.pop_float_to_indexed_var
|
||||
""")
|
||||
else ->
|
||||
throw AssemblyError("weird array type")
|
||||
}
|
||||
}
|
||||
|
||||
fun assignToRegister(reg: CpuRegister, value: Short?, identifier: IdentifierReference?) {
|
||||
if(value!=null) {
|
||||
asmgen.out(" ld${reg.toString().toLowerCase()} #${value.toHex()}")
|
||||
} else if(identifier!=null) {
|
||||
val name = asmgen.asmIdentifierName(identifier)
|
||||
asmgen.out(" ld${reg.toString().toLowerCase()} $name")
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
***/
|
||||
|
||||
***/
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user