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IR: fix byte to word assignment not doing value extension
This commit is contained in:
Irmen de Jong
parent
ef46fb2685
commit
97df33ab1a
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@ -161,7 +161,8 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val targetIdent = assignment.target.identifier
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val targetMemory = assignment.target.memory
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val targetArray = assignment.target.array
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val vmDt = codeGen.irType(assignment.value.type)
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val valueDt = codeGen.irType(assignment.value.type)
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val targetDt = codeGen.irType(assignment.target.type)
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val result = mutableListOf<IRCodeChunkBase>()
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var valueRegister = -1
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@ -169,30 +170,42 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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val zero = codeGen.isZero(assignment.value)
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if(!zero) {
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// calculate the assignment value
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if (vmDt == IRDataType.FLOAT) {
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if (valueDt == IRDataType.FLOAT) {
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val tr = expressionEval.translateExpression(assignment.value)
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valueFpRegister = tr.resultFpReg
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addToResult(result, tr, -1, valueFpRegister)
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} else {
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val extendByteToWord = if(targetDt != valueDt) {
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// usually an error EXCEPT when a byte is assigned to a word.
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if(targetDt==IRDataType.WORD && valueDt==IRDataType.BYTE)
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true
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else
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throw AssemblyError("assignment value and target dt mismatch")
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} else false
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if (assignment.value is PtMachineRegister) {
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valueRegister = (assignment.value as PtMachineRegister).register
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if(extendByteToWord)
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addInstr(result, IRInstruction(Opcode.EXT, IRDataType.BYTE, reg1=valueRegister), null)
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} else {
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val tr = expressionEval.translateExpression(assignment.value)
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valueRegister = tr.resultReg
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addToResult(result, tr, valueRegister, -1)
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if(extendByteToWord) {
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val opcode = if(assignment.value.type in SignedDatatypes) Opcode.EXTS else Opcode.EXT
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addInstr(result, IRInstruction(opcode, IRDataType.BYTE, reg1 = valueRegister), null)
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}
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}
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}
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}
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if(targetIdent!=null) {
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val instruction = if(zero) {
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IRInstruction(Opcode.STOREZM, vmDt, labelSymbol = targetIdent.name)
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IRInstruction(Opcode.STOREZM, targetDt, labelSymbol = targetIdent.name)
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} else {
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if (vmDt == IRDataType.FLOAT) {
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IRInstruction(Opcode.STOREM, vmDt, fpReg1 = valueFpRegister, labelSymbol = targetIdent.name)
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}
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if (targetDt == IRDataType.FLOAT)
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IRInstruction(Opcode.STOREM, targetDt, fpReg1 = valueFpRegister, labelSymbol = targetIdent.name)
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else
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IRInstruction(Opcode.STOREM, vmDt, reg1 = valueRegister, labelSymbol = targetIdent.name)
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IRInstruction(Opcode.STOREM, targetDt, reg1 = valueRegister, labelSymbol = targetIdent.name)
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}
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result += IRCodeChunk(null, null).also { it += instruction }
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return result
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@ -214,9 +227,9 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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if(zero) {
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// there's no STOREZIX instruction
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valueRegister = codeGen.registers.nextFree()
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code += IRInstruction(Opcode.LOAD, vmDt, reg1=valueRegister, immediate = 0)
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code += IRInstruction(Opcode.LOAD, targetDt, reg1=valueRegister, immediate = 0)
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}
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code += IRInstruction(Opcode.STOREIX, vmDt, reg1=valueRegister, reg2=idxReg, labelSymbol = variable)
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code += IRInstruction(Opcode.STOREIX, targetDt, reg1=valueRegister, reg2=idxReg, labelSymbol = variable)
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result += code
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return result
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}
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@ -225,59 +238,59 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val express
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if(zero) {
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZM, vmDt, labelSymbol = "$variable+$offset") }
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZM, targetDt, labelSymbol = "$variable+$offset") }
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result += chunk
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} else {
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val (code, indexReg) = loadIndexReg(targetArray, itemsize)
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result += code
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZX, vmDt, reg1=indexReg, labelSymbol = variable) }
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZX, targetDt, reg1=indexReg, labelSymbol = variable) }
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}
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} else {
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if(vmDt== IRDataType.FLOAT) {
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if(targetDt== IRDataType.FLOAT) {
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, vmDt, fpReg1 = valueFpRegister, labelSymbol = "$variable+$offset") }
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, targetDt, fpReg1 = valueFpRegister, labelSymbol = "$variable+$offset") }
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result += chunk
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} else {
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val (code, indexReg) = loadIndexReg(targetArray, itemsize)
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result += code
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREX, vmDt, reg1 = indexReg, fpReg1 = valueFpRegister, labelSymbol = variable) }
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREX, targetDt, reg1 = indexReg, fpReg1 = valueFpRegister, labelSymbol = variable) }
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}
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} else {
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if(fixedIndex!=null) {
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val offset = fixedIndex*itemsize
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, vmDt, reg1 = valueRegister, labelSymbol = "$variable+$offset") }
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, targetDt, reg1 = valueRegister, labelSymbol = "$variable+$offset") }
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result += chunk
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} else {
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val (code, indexReg) = loadIndexReg(targetArray, itemsize)
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result += code
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREX, vmDt, reg1 = valueRegister, reg2=indexReg, labelSymbol = variable) }
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREX, targetDt, reg1 = valueRegister, reg2=indexReg, labelSymbol = variable) }
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}
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}
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}
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return result
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}
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else if(targetMemory!=null) {
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require(vmDt== IRDataType.BYTE) { "must be byte type ${targetMemory.position}"}
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require(targetDt == IRDataType.BYTE) { "must be byte type ${targetMemory.position}"}
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if(zero) {
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if(targetMemory.address is PtNumber) {
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZM, vmDt, address = (targetMemory.address as PtNumber).number.toInt()) }
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZM, targetDt, address = (targetMemory.address as PtNumber).number.toInt()) }
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result += chunk
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} else {
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val tr = expressionEval.translateExpression(targetMemory.address)
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val addressReg = tr.resultReg
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addToResult(result, tr, tr.resultReg, -1)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, vmDt, reg1=addressReg) }
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREZI, targetDt, reg1=addressReg) }
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}
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} else {
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if(targetMemory.address is PtNumber) {
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, vmDt, reg1=valueRegister, address=(targetMemory.address as PtNumber).number.toInt()) }
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val chunk = IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREM, targetDt, reg1=valueRegister, address=(targetMemory.address as PtNumber).number.toInt()) }
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result += chunk
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} else {
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val tr = expressionEval.translateExpression(targetMemory.address)
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val addressReg = tr.resultReg
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addToResult(result, tr, tr.resultReg, -1)
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, vmDt, reg1=valueRegister, reg2=addressReg) }
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result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, targetDt, reg1=valueRegister, reg2=addressReg) }
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}
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}
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@ -4,7 +4,7 @@ TODO
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For next minor release
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^^^^^^^^^^^^^^^^^^^^^^
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- fix crash: uword remainder = seconds_uword % $0003 ==0
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- fix VM: void string.copy(".prg", &output_filename + string.length(output_filename))
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- fix VM problem with param passing: void string.copy(".prg", &output_filename + string.length(output_filename))
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- try to optimize newexpr a bit more
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...
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@ -5,9 +5,51 @@
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main {
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sub start() {
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str output_filename = "?????????\x00????????????"
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void string.copy(".prg", &output_filename + string.length(output_filename))
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txt.print(output_filename)
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str output_filename = "12345678\x00abcdefghij"
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void myprint2("hallo", &output_filename+string.length(output_filename))
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; ubyte length = string.length(output_filename)
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; txt.print_ub(length)
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; txt.nl()
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; txt.print_uw(&output_filename)
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; txt.nl()
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; output_filename[2]='!'
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; txt.print(output_filename)
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; txt.nl()
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;
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; void string_copy(".prg", &output_filename + string.length(output_filename))
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; txt.print(output_filename)
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}
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sub myprint2(str source1, str source2) {
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txt.print(source1)
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txt.nl()
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txt.print(source2)
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txt.nl()
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}
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sub string_copy(str source, str target) -> ubyte {
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; Copy a string to another, overwriting that one.
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; Returns the length of the string that was copied.
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; Often you don’t have to call this explicitly and can just write string1 = string2
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; but this function is useful if you’re dealing with addresses for instance.
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txt.print("src=")
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txt.print(source)
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txt.nl()
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txt.print("target=")
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txt.print(target)
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txt.nl()
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ubyte ix
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repeat 5 {
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ubyte qq=source[ix]
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txt.print_ub(qq)
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target[ix]=qq
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txt.spc()
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if qq==0 {
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txt.nl()
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return ix
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}
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ix++
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}
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}
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}
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@ -89,26 +89,26 @@ bgesr reg1, reg2, address - jump to location in program given by l
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ble reg1, value, address - jump to location in program given by location, if reg1 <= immediate value (unsigned)
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bles reg1, value, address - jump to location in program given by location, if reg1 <= immediate value (signed)
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( NOTE: there are no bltr/bler instructions because these are equivalent to bgtr/bger with the register operands swapped around.)
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sz reg1, reg2 - set reg1=1 if reg2==0, otherwise set reg1=0
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snz reg1, reg2 - set reg1=1 if reg2!=0, otherwise set reg1=0
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seq reg1, reg2 - set reg1=1 if reg1 == reg2, otherwise set reg1=0
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sne reg1, reg2 - set reg1=1 if reg1 != reg2, otherwise set reg1=0
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slt reg1, reg2 - set reg1=1 if reg1 < reg2 (unsigned), otherwise set reg1=0
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slts reg1, reg2 - set reg1=1 if reg1 < reg2 (signed), otherwise set reg1=0
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sle reg1, reg2 - set reg1=1 if reg1 <= reg2 (unsigned), otherwise set reg1=0
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sles reg1, reg2 - set reg1=1 if reg1 <= reg2 (signed), otherwise set reg1=0
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sgt reg1, reg2 - set reg1=1 if reg1 > reg2 (unsigned), otherwise set reg1=0
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sgts reg1, reg2 - set reg1=1 if reg1 > reg2 (signed), otherwise set reg1=0
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sge reg1, reg2 - set reg1=1 if reg1 >= reg2 (unsigned), otherwise set reg1=0
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sges reg1, reg2 - set reg1=1 if reg1 >= reg2 (signed), otherwise set reg1=0
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sz reg1, reg2 - set reg1=1.b if reg2==0, otherwise set reg1=0.b
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snz reg1, reg2 - set reg1=1.b if reg2!=0, otherwise set reg1=0.b
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seq reg1, reg2 - set reg1=1.b if reg1 == reg2, otherwise set reg1=0.b
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sne reg1, reg2 - set reg1=1.b if reg1 != reg2, otherwise set reg1=0.b
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slt reg1, reg2 - set reg1=1.b if reg1 < reg2 (unsigned), otherwise set reg1=0.b
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slts reg1, reg2 - set reg1=1.b if reg1 < reg2 (signed), otherwise set reg1=0.b
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sle reg1, reg2 - set reg1=1.b if reg1 <= reg2 (unsigned), otherwise set reg1=0.b
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sles reg1, reg2 - set reg1=1.b if reg1 <= reg2 (signed), otherwise set reg1=0.b
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sgt reg1, reg2 - set reg1=1.b if reg1 > reg2 (unsigned), otherwise set reg1=0.b
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sgts reg1, reg2 - set reg1=1.b if reg1 > reg2 (signed), otherwise set reg1=0.b
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sge reg1, reg2 - set reg1=1.b if reg1 >= reg2 (unsigned), otherwise set reg1=0.b
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sges reg1, reg2 - set reg1=1.b if reg1 >= reg2 (signed), otherwise set reg1=0.b
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ARITHMETIC
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----------
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All have type b or w or f. Note: result types are the same as operand types! E.g. byte*byte->byte.
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ext reg1 - reg1 = unsigned extension of reg1 (which in practice just means clearing the MSB / MSW) (ext.w not yet implemented as we don't have longs yet)
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exts reg1 - reg1 = signed extension of reg1 (byte to word, or word to long) (note: ext.w is not yet implemented as we don't have longs yet)
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ext reg1 - reg1 = unsigned extension of reg1 (which in practice just means clearing the MSB / MSW) (ext.w not yet implemented as we don't have longs yet)
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inc reg1 - reg1 = reg1+1
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incm address - memory at address += 1
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dec reg1 - reg1 = reg1-1
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