diff --git a/compilerAst/src/prog8/ast/AstToplevel.kt b/compilerAst/src/prog8/ast/AstToplevel.kt index 94b95e7af..1713f4934 100644 --- a/compilerAst/src/prog8/ast/AstToplevel.kt +++ b/compilerAst/src/prog8/ast/AstToplevel.kt @@ -244,8 +244,8 @@ interface Node { open class Module(final override var statements: MutableList, - final override val position: Position, - val source: SourceCode) : Node, INameScope { + final override val position: Position, + val source: SourceCode) : Node, INameScope { override lateinit var parent: Node lateinit var program: Program diff --git a/compilerAst/src/prog8/ast/statements/AstStatements.kt b/compilerAst/src/prog8/ast/statements/AstStatements.kt index 37382e134..5712d70b0 100644 --- a/compilerAst/src/prog8/ast/statements/AstStatements.kt +++ b/compilerAst/src/prog8/ast/statements/AstStatements.kt @@ -130,7 +130,7 @@ data class Label(override val name: String, override val position: Position) : S override fun toString()= "Label(name=$name, pos=$position)" } -open class Return(var value: Expression?, final override val position: Position) : Statement() { +class Return(var value: Expression?, final override val position: Position) : Statement() { override lateinit var parent: Node override fun linkParents(parent: Node) { @@ -171,7 +171,7 @@ enum class ZeropageWish { NOT_IN_ZEROPAGE } -open class VarDecl(val type: VarDeclType, +class VarDecl(val type: VarDeclType, private val declaredDatatype: DataType, val zeropage: ZeropageWish, var arraysize: ArrayIndex?, @@ -299,7 +299,7 @@ class ArrayIndex(var indexExpr: Expression, override fun copy() = ArrayIndex(indexExpr.copy(), position) } -open class Assignment(var target: AssignTarget, var value: Expression, final override val position: Position) : Statement() { +class Assignment(var target: AssignTarget, var value: Expression, final override val position: Position) : Statement() { override lateinit var parent: Node override fun linkParents(parent: Node) {