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vm: implementing rol/ror
This commit is contained in:
Irmen de Jong
parent
a8cf9f5cc4
commit
a0face4a28
@ -1,10 +1,7 @@
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package prog8.codegen.virtual
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import prog8.code.StStaticVariable
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import prog8.code.ast.PtBuiltinFunctionCall
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import prog8.code.ast.PtIdentifier
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import prog8.code.ast.PtNumber
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import prog8.code.ast.PtString
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import prog8.code.ast.*
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import prog8.code.core.DataType
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import prog8.vm.Opcode
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import prog8.vm.Syscall
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@ -154,6 +151,10 @@ internal class BuiltinFuncGen(private val codeGen: CodeGen, private val exprGen:
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code += VmCodeInstruction(Opcode.LOAD, VmDataType.BYTE, reg1=1, value=array.length)
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code += VmCodeInstruction(Opcode.SYSCALL, value=sortSyscall.ordinal)
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}
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"rol" -> RolRor2(Opcode.ROXL, call, resultRegister, code)
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"ror" -> RolRor2(Opcode.ROXR, call, resultRegister, code)
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"rol2" -> RolRor2(Opcode.ROL, call, resultRegister, code)
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"ror2" -> RolRor2(Opcode.ROR, call, resultRegister, code)
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else -> {
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TODO("builtinfunc ${call.name}")
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// code += VmCodeInstruction(Opcode.NOP))
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@ -179,4 +180,17 @@ internal class BuiltinFuncGen(private val codeGen: CodeGen, private val exprGen:
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return code
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}
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private fun RolRor2(opcode: Opcode, call: PtBuiltinFunctionCall, resultRegister: Int, code: VmCodeChunk) {
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// bit rotate left without carry, in-place
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val vmDt = codeGen.vmType(call.args[0].type)
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code += exprGen.translateExpression(call.args[0], resultRegister)
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code += VmCodeInstruction(opcode, vmDt, reg1=resultRegister)
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val assignment = PtAssignment(call.position)
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val target = PtAssignTarget(call.position)
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target.children.add(call.args[0])
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assignment.children.add(target)
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assignment.children.add(PtIdentifier(listOf(":vmreg-$resultRegister"), listOf(":vmreg-$resultRegister"), call.args[0].type, call.position))
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code += codeGen.translateNode(assignment)
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}
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}
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@ -57,7 +57,7 @@ class CodeGen(internal val program: PtProgram,
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}
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private fun translateNode(node: PtNode): VmCodeChunk {
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internal fun translateNode(node: PtNode): VmCodeChunk {
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val code = when(node) {
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is PtBlock -> translate(node)
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is PtSub -> translate(node)
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@ -80,6 +80,7 @@ class CodeGen(internal val program: PtProgram,
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is PtRepeatLoop -> translate(node)
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is PtLabel -> VmCodeChunk(VmCodeLabel(node.scopedName))
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is PtBreakpoint -> VmCodeChunk(VmCodeInstruction(Opcode.BREAKPOINT))
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is PtConditionalBranch -> translate(node)
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is PtAddressOf,
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is PtContainmentCheck,
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is PtMemoryByte,
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@ -99,7 +100,6 @@ class CodeGen(internal val program: PtProgram,
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is PtAsmSub -> throw AssemblyError("asmsub not supported on virtual machine target ${node.position}")
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is PtInlineAssembly -> throw AssemblyError("inline assembly not supported on virtual machine target ${node.position}")
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is PtIncludeBinary -> throw AssemblyError("inline binary data not supported on virtual machine target ${node.position}")
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is PtConditionalBranch -> throw AssemblyError("conditional branches not supported in vm target due to lack of cpu flags ${node.position}")
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else -> TODO("missing codegen for $node")
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}
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if(code.lines.isNotEmpty() && node.position.line!=0)
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@ -107,6 +107,33 @@ class CodeGen(internal val program: PtProgram,
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return code
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}
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private fun translate(branch: PtConditionalBranch): VmCodeChunk {
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val code = VmCodeChunk()
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val elseLabel = createLabelName()
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when(branch.condition) {
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BranchCondition.CS -> {
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code += VmCodeInstruction(Opcode.BSTCC, symbol = elseLabel)
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}
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BranchCondition.CC -> {
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code += VmCodeInstruction(Opcode.BSTCS, symbol = elseLabel)
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}
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else -> {
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throw AssemblyError("conditional branch ${branch.condition} not supported in vm target due to lack of cpu flags ${branch.position}")
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}
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}
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code += translateNode(branch.trueScope)
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if(branch.falseScope.children.isNotEmpty()) {
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val endLabel = createLabelName()
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code += VmCodeInstruction(Opcode.JUMP, symbol = endLabel)
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code += VmCodeLabel(elseLabel)
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code += translateNode(branch.falseScope)
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code += VmCodeLabel(endLabel)
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} else {
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code += VmCodeLabel(elseLabel)
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}
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return code
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}
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private fun translate(whenStmt: PtWhen): VmCodeChunk {
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if(whenStmt.choices.children.isEmpty())
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return VmCodeChunk()
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@ -90,11 +90,29 @@ sub print_ubhex (ubyte value, ubyte prefix) {
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sub print_ubbin (ubyte value, ubyte prefix) {
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; ---- print the ubyte in binary form
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; TODO use conv module?
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if prefix
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chrout('%')
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repeat 8 {
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rol(value)
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if_cc
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txt.chrout('0')
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else
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txt.chrout('1')
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}
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}
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sub print_uwbin (uword value, ubyte prefix) {
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; ---- print the uword in binary form
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; TODO use conv module?
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if prefix
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chrout('%')
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repeat 16 {
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rol(value)
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if_cc
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txt.chrout('0')
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else
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txt.chrout('1')
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}
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}
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sub print_uwhex (uword value, ubyte prefix) {
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@ -6,6 +6,7 @@
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main {
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sub start() {
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; a "pixelshader":
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void syscall1(8, 0) ; enable lo res creen
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ubyte shifter
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@ -14,7 +14,7 @@
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<keywords keywords="&;->;@;\$;and;as;asmsub;break;clobbers;do;downto;else;false;for;goto;if;if_cc;if_cs;if_eq;if_mi;if_ne;if_neg;if_nz;if_pl;if_pos;if_vc;if_vs;if_z;in;inline;not;or;repeat;return;romsub;step;sub;to;true;until;when;while;xor;~" ignore_case="false" />
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<keywords2 keywords="%address;%asm;%asmbinary;%asminclude;%breakpoint;%import;%launcher;%option;%output;%zeropage;%zpreserved;iso:;petscii:;sc:" />
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<keywords3 keywords="@requirezp;@shared;@zp;byte;const;float;str;ubyte;uword;void;word" />
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<keywords4 keywords="abs;acos;all;any;asin;atan;avg;callfar;callrom;ceil;cmp;cos;cos16;cos16u;cos8;cos8u;cosr16;cosr16u;cosr8;cosr8u;deg;floor;len;ln;log2;lsb;lsl;lsr;max;memory;min;mkword;msb;peek;peekw;poke;pokew;pop;popw;push;pushw;rad;reverse;rnd;rndf;rndw;rol;rol2;ror;ror2;round;rrestore;rrestorex;rsave;rsavex;sgn;sin;sin16;sin16u;sin8;sin8u;sinr16;sinr16u;sinr8;sinr8u;sizeof;sort;sqrt;sqrt16;sum;swap;tan;|>" />
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<keywords4 keywords="abs;acos;all;any;asin;atan;avg;callfar;callrom;ceil;cmp;cos;cos16;cos16u;cos8;cos8u;cosr16;cosr16u;cosr8;cosr8u;deg;floor;len;ln;log2;lsb;max;memory;min;mkword;msb;peek;peekw;poke;pokew;pop;popw;push;pushw;rad;reverse;rnd;rndf;rndw;rol;rol2;ror;ror2;round;rrestore;rrestorex;rsave;rsavex;sgn;sin;sin16;sin16u;sin8;sin8u;sinr16;sinr16u;sinr8;sinr8u;sizeof;sort;sqrt;sqrt16;sum;swap;tan;|>" />
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</highlighting>
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<extensionMap>
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<mapping ext="p8" />
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@ -7,6 +7,7 @@ Virtual machine:
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65536 virtual registers, 16 bits wide, can also be used as 8 bits. r0-r65535
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65536 bytes of memory. Thus memory pointers (addresses) are limited to 16 bits.
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Value stack, max 128 entries.
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Status registers: Carry.
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Instruction serialization format possibility:
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@ -59,8 +60,10 @@ return - restore last saved instruction location
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BRANCHING
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---------
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All have type b or w.
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All have type b or w except the branches that only check status bits.
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bstcc location - branch to location if Status bit Carry is Clear
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bstcs location - branch to location if Status bit Carry is Set
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bz reg1, location - branch to location if reg1 is zero
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bnz reg1, location - branch to location if reg1 is not zero
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beq reg1, reg2, location - jump to location in program given by location, if reg1 == reg2
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@ -84,7 +87,7 @@ sgts reg1, reg2, reg3 - set reg=1 if reg2 > reg3 (signed), ot
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sge reg1, reg2, reg3 - set reg=1 if reg2 >= reg3 (unsigned), otherwise set reg1=0
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sges reg1, reg2, reg3 - set reg=1 if reg2 >= reg3 (signed), otherwise set reg1=0
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TODO: support for the prog8 special branching instructions if_XX (bcc, bcs etc.)
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TODO: support for the other prog8 special branching instructions if_XX (bpl, bmi etc.)
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but we don't have any 'processor flags' whatsoever in the vm so it's a bit weird
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@ -105,7 +108,7 @@ mul reg1, reg2, reg3 - unsigned multiply reg1=reg2*reg3
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div reg1, reg2, reg3 - unsigned division reg1=reg2/reg3 note: division by zero yields max signed int $ff/$ffff
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mod reg1, reg2, reg3 - remainder (modulo) of unsigned division reg1=reg2%reg3 note: division by zero yields max signed int $ff/$ffff
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TODO signed mul/div/mod?
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NOTE: because mul/div are constrained (truncated) to remain in 8 or 16 bits, there is NO NEED for separate signed/unsigned mul and div instructions. The result is identical.
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LOGICAL/BITWISE
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@ -115,27 +118,29 @@ All have type b or w.
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and reg1, reg2, reg3 - reg1 = reg2 bitwise and reg3
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or reg1, reg2, reg3 - reg1 = reg2 bitwise or reg3
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xor reg1, reg2, reg3 - reg1 = reg2 bitwise xor reg3
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lsr reg1, reg2, reg3 - reg1 = shift reg2 right by reg3 bits
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asr reg1, reg2, reg3 - reg1 = shift reg2 right by reg3 bits (signed)
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lsl reg1, reg2, reg3 - reg1 = shift reg2 left by reg3 bits
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ror reg1, reg2, reg3 - reg1 = rotate reg2 right by reg3 bits, not using carry
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rol reg1, reg2, reg3 - reg1 = rotate reg2 left by reg3 bits, not using carry
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TODO also add ror/rol variants using the carry bit? These do map directly on 6502 and 68k instructions. But the VM doesn't have carry status bit yet.
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lsr reg1, reg2, reg3 - reg1 = shift reg2 right by reg3 bits + set Carry to shifted bit
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asr reg1, reg2, reg3 - reg1 = shift reg2 right by reg3 bits (signed) + set Carry to shifted bit
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lsl reg1, reg2, reg3 - reg1 = shift reg2 left by reg3 bits + set Carry to shifted bit
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ror reg1 - rotate reg1 right by 1 bits, not using carry + set Carry to shifted bit
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roxr reg1 - rotate reg1 right by 1 bits, using carry + set Carry to shifted bit
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rol reg1 - rotate reg1 left by 1bits, not using carry + set Carry to shifted bit
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roxl reg1 - rotate reg1 left by 1bits, using carry, + set Carry to shifted bit
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MISC
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----
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nop - do nothing
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breakpoint - trigger a breakpoint
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copy reg1, reg2, length - copy memory from ptrs in reg1 to reg3, length bytes
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copyz reg1, reg2 - copy memory from ptrs in reg1 to reg3, stop after first 0-byte
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swap [b, w] reg1 - swap lsb and msb in register reg1 (16 bits) or lsw and msw (32 bits)
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swapreg reg1, reg2 - swap values in reg1 and reg2
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concat [b, w] reg1, reg2, reg3 - reg1 = concatenated lsb/lsw of reg2 and lsb/lsw of reg3 into new word or int (int not yet implemented, requires 32bits regs)
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push [b, w] reg1 - push value in reg1 on the stack
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pop [b, w] reg1 - pop value from stack into reg1
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clc - clear Carry status bit
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sec - set Carry status bit
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nop - do nothing
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breakpoint - trigger a breakpoint
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copy reg1, reg2, length - copy memory from ptrs in reg1 to reg3, length bytes
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copyz reg1, reg2 - copy memory from ptrs in reg1 to reg3, stop after first 0-byte
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swap [b, w] reg1 - swap lsb and msb in register reg1 (16 bits) or lsw and msw (32 bits)
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swapreg reg1, reg2 - swap values in reg1 and reg2
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concat [b, w] reg1, reg2, reg3 - reg1 = concatenated lsb/lsw of reg2 and lsb/lsw of reg3 into new word or int (int not yet implemented, requires 32bits regs)
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push [b, w] reg1 - push value in reg1 on the stack
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pop [b, w] reg1 - pop value from stack into reg1
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*/
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@ -159,6 +164,9 @@ enum class Opcode {
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CALLI,
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SYSCALL,
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RETURN,
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BSTCC,
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BSTCS,
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BZ,
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BNZ,
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BEQ,
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@ -202,8 +210,12 @@ enum class Opcode {
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LSR,
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LSL,
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ROR,
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ROXR,
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ROL,
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ROXL,
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CLC,
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SEC,
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PUSH,
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POP,
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SWAP,
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@ -249,6 +261,11 @@ data class Instruction(
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format.reg3 && reg3==null)
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throw IllegalArgumentException("missing a register")
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if(!format.reg1 && reg1!=null ||
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!format.reg2 && reg2!=null ||
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!format.reg3 && reg3!=null)
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throw IllegalArgumentException("too many registers")
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if(format.value && (value==null && symbol==null))
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throw IllegalArgumentException("missing a value or symbol")
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}
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@ -313,6 +330,9 @@ val instructionFormats = mutableMapOf(
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Opcode.CALLI to InstructionFormat(NN, true, false, false, false),
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Opcode.SYSCALL to InstructionFormat(NN, false, false, false, true ),
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Opcode.RETURN to InstructionFormat(NN, false, false, false, false),
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Opcode.BSTCC to InstructionFormat(NN, false, false, false, true ),
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Opcode.BSTCS to InstructionFormat(NN, false, false, false, true ),
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Opcode.BZ to InstructionFormat(BW, true, false, false, true ),
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Opcode.BNZ to InstructionFormat(BW, true, false, false, true ),
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Opcode.BEQ to InstructionFormat(BW, true, true, false, true ),
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@ -355,8 +375,10 @@ val instructionFormats = mutableMapOf(
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Opcode.ASR to InstructionFormat(BW, true, true, true, false),
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Opcode.LSR to InstructionFormat(BW, true, true, true, false),
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Opcode.LSL to InstructionFormat(BW, true, true, true, false),
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Opcode.ROR to InstructionFormat(BW, true, true, true, false),
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Opcode.ROL to InstructionFormat(BW, true, true, true, false),
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Opcode.ROR to InstructionFormat(BW, true, false, false, false),
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Opcode.ROXR to InstructionFormat(BW, true, false, false, false),
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Opcode.ROL to InstructionFormat(BW, true, false, false, false),
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Opcode.ROXL to InstructionFormat(BW, true, false, false, false),
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Opcode.COPY to InstructionFormat(NN, true, true, false, true ),
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Opcode.COPYZ to InstructionFormat(NN, true, true, false, false),
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@ -364,5 +386,7 @@ val instructionFormats = mutableMapOf(
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Opcode.PUSH to InstructionFormat(BW, true, false, false, false),
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Opcode.POP to InstructionFormat(BW, true, false, false, false),
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Opcode.CONCAT to InstructionFormat(BW, true, true, true, false),
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Opcode.CLC to InstructionFormat(NN, false, false, false, false),
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Opcode.SEC to InstructionFormat(NN, false, false, false, false),
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Opcode.BREAKPOINT to InstructionFormat(NN, false, false, false, false)
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)
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@ -19,6 +19,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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val valueStack = Stack<Int>() // max 128 entries
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var pc = 0
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var stepCount = 0
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var statusCarry = false
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init {
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if(program.size>65536)
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@ -58,6 +59,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc = 0
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stepCount = 0
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callStack.clear()
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statusCarry = false
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}
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fun exit() {
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@ -97,6 +99,8 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.CALLI -> InsCALLI(ins)
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Opcode.SYSCALL -> InsSYSCALL(ins)
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Opcode.RETURN -> InsRETURN()
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Opcode.BSTCC -> InsBSTCC(ins)
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Opcode.BSTCS -> InsBSTCS(ins)
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Opcode.BZ -> InsBZ(ins)
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Opcode.BNZ -> InsBNZ(ins)
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Opcode.BEQ -> InsBEQ(ins)
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@ -138,8 +142,10 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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Opcode.ASR -> InsASR(ins)
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Opcode.LSR -> InsLSR(ins)
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Opcode.LSL -> InsLSL(ins)
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Opcode.ROR -> InsROR(ins)
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Opcode.ROL -> InsROL(ins)
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Opcode.ROR -> InsROR(ins, false)
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Opcode.ROXR -> InsROR(ins, true)
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Opcode.ROL -> InsROL(ins, false)
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Opcode.ROXL -> InsROL(ins, true)
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Opcode.SWAP -> InsSWAP(ins)
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Opcode.CONCAT -> InsCONCAT(ins)
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Opcode.PUSH -> InsPUSH(ins)
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@ -312,6 +318,20 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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pc = callStack.pop()
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}
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private fun InsBSTCC(i: Instruction) {
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if(!statusCarry)
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pc = i.value!!
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else
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pc++
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}
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private fun InsBSTCS(i: Instruction) {
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if(statusCarry)
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pc = i.value!!
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else
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pc++
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}
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private fun InsBZ(i: Instruction) {
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when(i.type!!) {
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VmDataType.BYTE -> {
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@ -666,6 +686,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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private fun InsASR(i: Instruction) {
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val (left: Int, right: Int) = getLogicalOperandsS(i)
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statusCarry = (left and 1)!=0
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when(i.type!!) {
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VmDataType.BYTE -> registers.setSB(i.reg1!!, (left shr right).toByte())
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VmDataType.WORD -> registers.setSW(i.reg1!!, (left shr right).toShort())
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@ -675,6 +696,7 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
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private fun InsLSR(i: Instruction) {
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val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
statusCarry = (left and 1u)!=0u
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left shr right.toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left shr right.toInt()).toUShort())
|
||||
@ -685,28 +707,72 @@ class VirtualMachine(val memory: Memory, program: List<Instruction>) {
|
||||
private fun InsLSL(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left shl right.toInt()).toUByte())
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left shl right.toInt()).toUShort())
|
||||
VmDataType.BYTE -> {
|
||||
statusCarry = (left and 0x80u)!=0u
|
||||
registers.setUB(i.reg1!!, (left shl right.toInt()).toUByte())
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
statusCarry = (left and 0x8000u)!=0u
|
||||
registers.setUW(i.reg1!!, (left shl right.toInt()).toUShort())
|
||||
}
|
||||
}
|
||||
pc++
|
||||
}
|
||||
|
||||
private fun InsROR(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left.rotateRight(right.toInt()).toUByte()))
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left.rotateRight(right.toInt()).toUShort()))
|
||||
private fun InsROR(i: Instruction, useCarry: Boolean) {
|
||||
val newStatusCarry: Boolean
|
||||
when (i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val orig = registers.getUB(i.reg1!!)
|
||||
newStatusCarry = (orig.toInt() and 1) != 0
|
||||
val rotated: UByte = if (useCarry) {
|
||||
val carry = if (statusCarry) 0x80u else 0x00u
|
||||
(orig.toUInt().rotateRight(1) or carry).toUByte()
|
||||
} else
|
||||
orig.rotateRight(1)
|
||||
registers.setUB(i.reg1, rotated)
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val orig = registers.getUW(i.reg1!!)
|
||||
newStatusCarry = (orig.toInt() and 1) != 0
|
||||
val rotated: UShort = if (useCarry) {
|
||||
val carry = if (statusCarry) 0x8000u else 0x0000u
|
||||
(orig.toUInt().rotateRight(1) or carry).toUShort()
|
||||
} else
|
||||
orig.rotateRight(1)
|
||||
registers.setUW(i.reg1, rotated)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
statusCarry = newStatusCarry
|
||||
}
|
||||
|
||||
private fun InsROL(i: Instruction) {
|
||||
val (left: UInt, right: UInt) = getLogicalOperandsU(i)
|
||||
when(i.type!!) {
|
||||
VmDataType.BYTE -> registers.setUB(i.reg1!!, (left.rotateLeft(right.toInt()).toUByte()))
|
||||
VmDataType.WORD -> registers.setUW(i.reg1!!, (left.rotateLeft(right.toInt()).toUShort()))
|
||||
private fun InsROL(i: Instruction, useCarry: Boolean) {
|
||||
val newStatusCarry: Boolean
|
||||
when (i.type!!) {
|
||||
VmDataType.BYTE -> {
|
||||
val orig = registers.getUB(i.reg1!!)
|
||||
newStatusCarry = (orig.toInt() and 0x80) != 0
|
||||
val rotated: UByte = if (useCarry) {
|
||||
val carry = if (statusCarry) 1u else 0u
|
||||
(orig.toUInt().rotateLeft(1) or carry).toUByte()
|
||||
} else
|
||||
orig.rotateLeft(1)
|
||||
registers.setUB(i.reg1, rotated)
|
||||
}
|
||||
VmDataType.WORD -> {
|
||||
val orig = registers.getUW(i.reg1!!)
|
||||
newStatusCarry = (orig.toInt() and 0x8000) != 0
|
||||
val rotated: UShort = if (useCarry) {
|
||||
val carry = if (statusCarry) 1u else 0u
|
||||
(orig.toUInt().rotateLeft(1) or carry).toUShort()
|
||||
} else
|
||||
orig.rotateLeft(1)
|
||||
registers.setUW(i.reg1, rotated)
|
||||
}
|
||||
}
|
||||
pc++
|
||||
statusCarry = newStatusCarry
|
||||
}
|
||||
|
||||
private fun InsSWAP(i: Instruction) {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user