From a2133f61a875e7c5eeb7417e74a198e6a50507d1 Mon Sep 17 00:00:00 2001 From: Irmen de Jong Date: Tue, 14 Mar 2023 00:59:15 +0100 Subject: [PATCH] get rid of all the require() checks that test result regs to be different --- .../codegen/intermediate/BuiltinFuncGen.kt | 4 ---- .../codegen/intermediate/ExpressionGen.kt | 23 ------------------- .../prog8/codegen/intermediate/IRCodeGen.kt | 5 ---- docs/source/todo.rst | 4 ++-- 4 files changed, 2 insertions(+), 34 deletions(-) diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt index 775c0eb7d..f2b5ba232 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/BuiltinFuncGen.kt @@ -50,7 +50,6 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe val leftTr = exprGen.translateExpression(call.args[0]) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = exprGen.translateExpression(call.args[1]) - require(leftTr.resultReg!=rightTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) val dt = codeGen.irType(call.args[0].type) result += IRCodeChunk(null, null).also { @@ -262,7 +261,6 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe val msbTr = exprGen.translateExpression(call.args[0]) addToResult(result, msbTr, msbTr.resultReg, -1) val lsbTr = exprGen.translateExpression(call.args[1]) - require(lsbTr.resultReg!=msbTr.resultReg) addToResult(result, lsbTr, lsbTr.resultReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.CONCAT, IRDataType.BYTE, reg1 = lsbTr.resultReg, reg2 = msbTr.resultReg) @@ -297,7 +295,6 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe val addressTr = exprGen.translateExpression(call.args[0]) addToResult(result, addressTr, addressTr.resultReg, -1) val valueTr = exprGen.translateExpression(call.args[1]) - require(valueTr.resultReg!=addressTr.resultReg) addToResult(result, valueTr, valueTr.resultReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, IRDataType.WORD, reg1 = valueTr.resultReg, reg2 = addressTr.resultReg) @@ -334,7 +331,6 @@ internal class BuiltinFuncGen(private val codeGen: IRCodeGen, private val exprGe val addressTr = exprGen.translateExpression(call.args[0]) addToResult(result, addressTr, addressTr.resultReg, -1) val valueTr = exprGen.translateExpression(call.args[1]) - require(valueTr.resultReg!=addressTr.resultReg) addToResult(result, valueTr, valueTr.resultReg, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.STOREI, IRDataType.BYTE, reg1 = valueTr.resultReg, reg2 = addressTr.resultReg) diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt index cfba5e091..61c18b58e 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/ExpressionGen.kt @@ -440,7 +440,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) val resultRegister = codeGen.registers.nextFree() addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) @@ -458,7 +457,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, SyscallRegisterBase, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) @@ -475,7 +473,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) val ins = if (signed) { if (greaterEquals) Opcode.SGES else Opcode.SGTS @@ -499,7 +496,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) val resultRegister = codeGen.registers.nextFree() addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=resultRegister, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) @@ -517,7 +513,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, SyscallRegisterBase, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) @@ -534,7 +529,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) val ins = if (signed) { if (lessEquals) Opcode.SLES else Opcode.SLTS @@ -553,7 +547,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) val resultRegister = codeGen.registers.nextFree() if (notEquals) { @@ -573,7 +566,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, SyscallRegisterBase, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, SyscallRegisterBase+1, -1) result += IRCodeChunk(null, null).also { it += IRInstruction(Opcode.SYSCALL, value = IMSyscall.COMPARE_STRINGS.number) @@ -595,7 +587,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) val opcode = if (notEquals) Opcode.SNE else Opcode.SEQ addInstr(result, IRInstruction(opcode, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null) @@ -617,7 +608,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) val opc = if (signed) Opcode.ASRN else Opcode.LSRN addInstr(result, IRInstruction(opc, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null) @@ -658,7 +648,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, IRInstruction(Opcode.LSLN, vmDt, reg1=leftTr.resultReg, rightTr.resultReg), null) ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1) @@ -696,7 +685,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, IRInstruction(Opcode.XORR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null) ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1) @@ -726,7 +714,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, IRInstruction(Opcode.ANDR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null) ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1) @@ -756,7 +743,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, IRInstruction(Opcode.ORR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null) ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1) @@ -787,7 +773,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, IRInstruction(Opcode.MODR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null) ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1) @@ -808,7 +793,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) addInstr(result, if(signed) IRInstruction(Opcode.DIVSR, vmDt, fpReg1 = leftTr.resultFpReg, fpReg2=rightTr.resultFpReg) @@ -838,7 +822,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, if (signed) IRInstruction(Opcode.DIVSR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg) @@ -921,7 +904,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) addInstr(result, IRInstruction(Opcode.MULR, vmDt, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) ExpressionCodeResult(result, vmDt, -1, leftTr.resultFpReg) @@ -943,7 +925,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, IRInstruction(Opcode.MULR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null) ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1) @@ -1003,7 +984,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) addInstr(result, IRInstruction(Opcode.SUBR, vmDt, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) ExpressionCodeResult(result, vmDt, -1, leftTr.resultFpReg) @@ -1026,7 +1006,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, IRInstruction(Opcode.SUBR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null) ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1) @@ -1100,7 +1079,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) addInstr(result, IRInstruction(Opcode.ADDR, vmDt, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) ExpressionCodeResult(result, vmDt, -1, leftTr.resultFpReg) @@ -1129,7 +1107,6 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) { val leftTr = translateExpression(binExpr.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = translateExpression(binExpr.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) addInstr(result, IRInstruction(Opcode.ADDR, vmDt, reg1 = leftTr.resultReg, reg2 = rightTr.resultReg), null) ExpressionCodeResult(result, vmDt, leftTr.resultReg, -1) diff --git a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt index 34045a3a6..184b1c7dd 100644 --- a/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt +++ b/codeGenIntermediate/src/prog8/codegen/intermediate/IRCodeGen.kt @@ -530,7 +530,6 @@ class IRCodeGen( val toTr = expressionEval.translateExpression(iterable.to) addToResult(result, toTr, toTr.resultReg, -1) val fromTr = expressionEval.translateExpression(iterable.from) - require(fromTr.resultReg!=toTr.resultReg) addToResult(result, fromTr, fromTr.resultReg, -1) val labelAfterFor = createLabelName() @@ -916,7 +915,6 @@ class IRCodeGen( val leftTr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = expressionEval.translateExpression(ifElse.condition.right) - require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) result += IRCodeChunk(null,null).also { val compResultReg = registers.nextFree() @@ -985,7 +983,6 @@ class IRCodeGen( val leftTr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = expressionEval.translateExpression(ifElse.condition.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) val opcode: Opcode val firstReg: Int @@ -1105,7 +1102,6 @@ class IRCodeGen( val leftTr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, leftTr, -1, leftTr.resultFpReg) val rightTr = expressionEval.translateExpression(ifElse.condition.right) - require(rightTr.resultFpReg!=leftTr.resultFpReg) addToResult(result, rightTr, -1, rightTr.resultFpReg) val compResultReg = registers.nextFree() addInstr(result, IRInstruction(Opcode.FCOMP, IRDataType.FLOAT, reg1=compResultReg, fpReg1 = leftTr.resultFpReg, fpReg2 = rightTr.resultFpReg), null) @@ -1140,7 +1136,6 @@ class IRCodeGen( val leftTr = expressionEval.translateExpression(ifElse.condition.left) addToResult(result, leftTr, leftTr.resultReg, -1) val rightTr = expressionEval.translateExpression(ifElse.condition.right) - require(rightTr.resultReg!=leftTr.resultReg) addToResult(result, rightTr, rightTr.resultReg, -1) when (ifElse.condition.operator) { "==" -> { diff --git a/docs/source/todo.rst b/docs/source/todo.rst index ea9cc158c..180660dc9 100644 --- a/docs/source/todo.rst +++ b/docs/source/todo.rst @@ -3,8 +3,8 @@ TODO For next minor release ^^^^^^^^^^^^^^^^^^^^^^ -- bouncegfx is larger than with 8.10 -- get rid of all the require() checks that test result regs to be different +- array[var] = 22 generates lareger code now in IR (-> bouncegfx is larger than with 8.10) +- array[var] *= -1 generates lareger code now in IR (-> bouncegfx is larger than with 8.10) ...