From a798fe72d33e1289f8c7ca7a9f573fdf3b142891 Mon Sep 17 00:00:00 2001 From: Irmen de Jong Date: Sat, 15 Jan 2022 13:49:49 +0100 Subject: [PATCH] cx16 reserved zp vars (virtual registers) --- .../codegen/target/cx16/CX16MachineDefinition.kt | 15 --------------- .../src/prog8/codegen/target/cx16/CX16Zeropage.kt | 11 +++++++++++ compiler/test/ZeropageTests.kt | 12 ++++++++++++ .../src/prog8/compilerinterface/Zeropage.kt | 2 +- docs/source/todo.rst | 1 - 5 files changed, 24 insertions(+), 17 deletions(-) diff --git a/codeGeneration/src/prog8/codegen/target/cx16/CX16MachineDefinition.kt b/codeGeneration/src/prog8/codegen/target/cx16/CX16MachineDefinition.kt index eaf7a2747..f8a2bd689 100644 --- a/codeGeneration/src/prog8/codegen/target/cx16/CX16MachineDefinition.kt +++ b/codeGeneration/src/prog8/codegen/target/cx16/CX16MachineDefinition.kt @@ -68,21 +68,6 @@ class CX16MachineDefinition: IMachineDefinition { override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0x9f00u..0x9fffu - - // TODO integrate this in the internal list of allocated zp variables: -// override fun getPreallocatedZeropageVars(): Map> { -// val vars = mutableMapOf>() -// for(reg in 0..15) { -// vars["cx16.r${reg}"] = (2+reg*2).toUInt() to DataType.UWORD // cx16.r0 .. cx16.r15 -// vars["cx16.r${reg}s"] = (2+reg*2).toUInt() to DataType.WORD // cx16.r0s .. cx16.r15s -// vars["cx16.r${reg}L"] = (2+reg*2).toUInt() to DataType.UBYTE // cx16.r0L .. cx16.r15L -// vars["cx16.r${reg}H"] = (3+reg*2).toUInt() to DataType.UBYTE // cx16.r0H .. cx16.r15H -// vars["cx16.r${reg}sL"] = (2+reg*2).toUInt() to DataType.BYTE // cx16.r0sL .. cx16.r15sL -// vars["cx16.r${reg}sH"] = (3+reg*2).toUInt() to DataType.BYTE // cx16.r0sH .. cx16.r15sH -// } -// return vars -// } - override fun initializeZeropage(compilerOptions: CompilationOptions) { zeropage = CX16Zeropage(compilerOptions) } diff --git a/codeGeneration/src/prog8/codegen/target/cx16/CX16Zeropage.kt b/codeGeneration/src/prog8/codegen/target/cx16/CX16Zeropage.kt index 3224ef34f..a08be1add 100644 --- a/codeGeneration/src/prog8/codegen/target/cx16/CX16Zeropage.kt +++ b/codeGeneration/src/prog8/codegen/target/cx16/CX16Zeropage.kt @@ -1,5 +1,6 @@ package prog8.codegen.target.cx16 +import prog8.ast.base.DataType import prog8.compilerinterface.CompilationOptions import prog8.compilerinterface.InternalCompilerException import prog8.compilerinterface.Zeropage @@ -37,5 +38,15 @@ class CX16Zeropage(options: CompilationOptions) : Zeropage(options) { } removeReservedFromFreePool() + + for(reg in 0..15) { + allocatedVariables["cx16.r${reg}"] = ((2+reg*2).toUInt() to 2) to DataType.UWORD // cx16.r0 .. cx16.r15 + allocatedVariables["cx16.r${reg}s"] = ((2+reg*2).toUInt() to 2) to DataType.WORD // cx16.r0s .. cx16.r15s + allocatedVariables["cx16.r${reg}L"] = ((2+reg*2).toUInt() to 1) to DataType.UBYTE // cx16.r0L .. cx16.r15L + allocatedVariables["cx16.r${reg}H"] = ((3+reg*2).toUInt() to 1) to DataType.UBYTE // cx16.r0H .. cx16.r15H + allocatedVariables["cx16.r${reg}sL"] = ((2+reg*2).toUInt() to 1) to DataType.BYTE // cx16.r0sL .. cx16.r15sL + allocatedVariables["cx16.r${reg}sH"] = ((3+reg*2).toUInt() to 1) to DataType.BYTE // cx16.r0sH .. cx16.r15sH + } + } } \ No newline at end of file diff --git a/compiler/test/ZeropageTests.kt b/compiler/test/ZeropageTests.kt index 6b1553793..ce169bf9b 100644 --- a/compiler/test/ZeropageTests.kt +++ b/compiler/test/ZeropageTests.kt @@ -11,6 +11,7 @@ import io.kotest.matchers.collections.shouldBeIn import io.kotest.matchers.collections.shouldNotBeIn import io.kotest.matchers.comparables.shouldBeGreaterThan import io.kotest.matchers.shouldBe +import io.kotest.matchers.shouldNotBe import prog8.ast.base.DataType import prog8.ast.expressions.Expression import prog8.ast.statements.RegisterOrStatusflag @@ -287,4 +288,15 @@ class TestCx16Zeropage: FunSpec({ 0x02u shouldNotBeIn zp1.free 0x21u shouldNotBeIn zp1.free } + + test("preallocated zp vars") { + val zp1 = CX16Zeropage(CompilationOptions(OutputType.RAW, LauncherType.NONE, ZeropageType.FULL, emptyList(), false, false, Cx16Target)) + zp1.allocatedZeropageVariable("test") shouldBe null + zp1.allocatedZeropageVariable("cx16.r0") shouldNotBe null + zp1.allocatedZeropageVariable("cx16.r15") shouldNotBe null + zp1.allocatedZeropageVariable("cx16.r0L") shouldNotBe null + zp1.allocatedZeropageVariable("cx16.r15L") shouldNotBe null + zp1.allocatedZeropageVariable("cx16.r0sH") shouldNotBe null + zp1.allocatedZeropageVariable("cx16.r15sH") shouldNotBe null + } }) diff --git a/compilerInterfaces/src/prog8/compilerinterface/Zeropage.kt b/compilerInterfaces/src/prog8/compilerinterface/Zeropage.kt index cd761dbd1..683d56161 100644 --- a/compilerInterfaces/src/prog8/compilerinterface/Zeropage.kt +++ b/compilerInterfaces/src/prog8/compilerinterface/Zeropage.kt @@ -104,5 +104,5 @@ abstract class Zeropage(protected val options: CompilationOptions) { fun allocatedZeropageVariable(scopedname: String): Pair, DataType>? = allocatedVariables[scopedname] - private val allocatedVariables = mutableMapOf, DataType>>() + protected val allocatedVariables = mutableMapOf, DataType>>() } diff --git a/docs/source/todo.rst b/docs/source/todo.rst index 146c17122..9cc830f85 100644 --- a/docs/source/todo.rst +++ b/docs/source/todo.rst @@ -4,7 +4,6 @@ TODO For next compiler release (7.7) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - fix array and string initialization in zeropage -- fix cx16 zeropage preallocated vars (virtual regs) - fix ForloopAsmGen zp allocation handling - check all examples if they still run correctly (c64 + cx16) - document check: arrays and strings can also be placed in zeropage (but almost never should, due to size!)