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https://github.com/irmen/prog8.git
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ir: more optimized inplace array assignments
This commit is contained in:
Irmen de Jong committed
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a14a8f4e62
commit
a7b14c2931
3 files changed
+490
-15
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@@ -1453,7 +1453,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val exprGen
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return result
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}
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private fun operatorDivideInplace(symbol: String?, array: PtArrayIndexer?, constAddress: UInt?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks? {
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private fun operatorDivideInplace(symbol: String?, array: PtArrayIndexer?, constAddress: UInt?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks {
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if(array!=null) {
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if(array.splitWords)
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return operatorDivideInplaceSplitArray(array, operand, signed)
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@@ -1551,8 +1551,46 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val exprGen
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}
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return result
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}
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if(constAddress==null && memory!=null)
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return null // TODO("optimized memory in-place /"")
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if(constAddress==null && memory!=null) {
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val resultVar = mutableListOf<IRCodeChunkBase>()
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val addrTr = exprGen.translateExpression(memory.address)
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addToResult(resultVar, addrTr, addrTr.resultReg, -1)
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val addressReg = addrTr.resultReg
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if(vmDt==IRDataType.FLOAT) {
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val tr = exprGen.translateExpression(operand)
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addToResult(resultVar, tr, -1, tr.resultFpReg)
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val loadReg = codeGen.registers.next(IRDataType.FLOAT)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADI, vmDt, fpReg1=RegisterNum(loadReg), reg1=addressReg, immediate=0)
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it += IRInstruction(Opcode.DIVR, vmDt, fpReg1=RegisterNum(loadReg), fpReg2=RegisterNum(tr.resultFpReg))
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it += IRInstruction(Opcode.STOREI, vmDt, fpReg1=RegisterNum(loadReg), reg1=addressReg, immediate=0)
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}
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} else {
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val loadReg = codeGen.registers.next(vmDt)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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val constVal = (operand as? PtNumber)?.number?.toInt()
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if(constVal!=null) {
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val constReg = codeGen.registers.next(vmDt)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, vmDt, reg1=constReg, immediate=constVal)
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val opc = if(signed) Opcode.DIVSR else Opcode.DIVR
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it += IRInstruction(opc, vmDt, reg1=loadReg, reg2=constReg)
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it += IRInstruction(Opcode.STOREI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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} else {
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val opTr = exprGen.translateExpression(operand)
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addToResult(resultVar, opTr, opTr.resultReg, -1)
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resultVar += IRCodeChunk(null, null).also {
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val opc = if(signed) Opcode.DIVSR else Opcode.DIVR
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it += IRInstruction(opc, vmDt, reg1=loadReg, reg2=opTr.resultReg)
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it += IRInstruction(Opcode.STOREI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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}
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}
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return resultVar
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}
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val result = mutableListOf<IRCodeChunkBase>()
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val constFactorRight = operand as? PtNumber
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@@ -1665,8 +1703,46 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val exprGen
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}
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return result
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}
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if(constAddress==null && memory!=null)
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return null // TODO("optimized memory in-place *"")
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if(constAddress==null && memory!=null) {
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val resultVar = mutableListOf<IRCodeChunkBase>()
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val addrTr = exprGen.translateExpression(memory.address)
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addToResult(resultVar, addrTr, addrTr.resultReg, -1)
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val addressReg = addrTr.resultReg
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if(vmDt==IRDataType.FLOAT) {
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val tr = exprGen.translateExpression(operand)
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addToResult(resultVar, tr, -1, tr.resultFpReg)
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val loadReg = codeGen.registers.next(IRDataType.FLOAT)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADI, vmDt, fpReg1=RegisterNum(loadReg), reg1=addressReg, immediate=0)
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it += IRInstruction(Opcode.MULR, vmDt, fpReg1=RegisterNum(loadReg), fpReg2=RegisterNum(tr.resultFpReg))
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it += IRInstruction(Opcode.STOREI, vmDt, fpReg1=RegisterNum(loadReg), reg1=addressReg, immediate=0)
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}
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} else {
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val loadReg = codeGen.registers.next(vmDt)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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val constVal = (operand as? PtNumber)?.number?.toInt()
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if(constVal!=null) {
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val constReg = codeGen.registers.next(vmDt)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, vmDt, reg1=constReg, immediate=constVal)
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val opc = if(signed) Opcode.MULSR else Opcode.MULR
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it += IRInstruction(opc, vmDt, reg1=loadReg, reg2=constReg)
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it += IRInstruction(Opcode.STOREI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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} else {
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val opTr = exprGen.translateExpression(operand)
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addToResult(resultVar, opTr, opTr.resultReg, -1)
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resultVar += IRCodeChunk(null, null).also {
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val opc = if(signed) Opcode.MULSR else Opcode.MULR
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it += IRInstruction(opc, vmDt, reg1=loadReg, reg2=opTr.resultReg)
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it += IRInstruction(Opcode.STOREI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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}
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}
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return resultVar
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}
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val result = mutableListOf<IRCodeChunkBase>()
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val constFactorRight = operand as? PtNumber
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@@ -2320,10 +2396,87 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val exprGen
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}
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return result
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}
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return null // TODO("optimized >> in array")
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// optimized handling for variable index or variable shift count (non-split)
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if(!array.splitWords) {
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val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
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val resultVar = mutableListOf<IRCodeChunkBase>()
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val indexTr = exprGen.translateExpression(array.index)
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addToResult(resultVar, indexTr, indexTr.resultReg, -1)
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val (indexReg, indexDt) = normalizeArrayIndex(resultVar, indexTr)
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if(eltSize > 1)
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resultVar += codeGen.multiplyByConst(indexDt, indexReg, eltSize)
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val loadReg = codeGen.registers.next(vmDt)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADX, vmDt, reg1=loadReg, reg2=indexReg, labelSymbol=array.variable!!.name)
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}
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val constShift = operand.asConstInteger()
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if(constShift!=null) {
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if(constShift==1) {
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val opc = if(signed) Opcode.ASR else Opcode.LSR
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(opc, vmDt, reg1=loadReg)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1=loadReg, reg2=indexReg, labelSymbol=array.variable!!.name)
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}
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} else {
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val shiftReg = codeGen.registers.next(IRDataType.BYTE)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=shiftReg, immediate=constShift and 255)
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val opc = if(signed) Opcode.ASRN else Opcode.LSRN
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it += IRInstruction(opc, vmDt, reg1=loadReg, reg2=shiftReg)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1=loadReg, reg2=indexReg, labelSymbol=array.variable!!.name)
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}
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}
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} else {
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val shiftTr = exprGen.translateExpression(operand)
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addToResult(resultVar, shiftTr, shiftTr.resultReg, -1)
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resultVar += IRCodeChunk(null, null).also {
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val opc = if(signed) Opcode.ASRN else Opcode.LSRN
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it += IRInstruction(opc, vmDt, reg1=loadReg, reg2=shiftTr.resultReg)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1=loadReg, reg2=indexReg, labelSymbol=array.variable!!.name)
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}
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}
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return resultVar
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}
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return null
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}
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if(constAddress==null && memory!=null) {
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// optimized memory in-place >> with variable address
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val resultVar = mutableListOf<IRCodeChunkBase>()
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val addrTr = exprGen.translateExpression(memory.address)
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addToResult(resultVar, addrTr, addrTr.resultReg, -1)
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val addressReg = addrTr.resultReg
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val loadReg = codeGen.registers.next(vmDt)
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val constShift = operand.asConstInteger()
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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if(constShift!=null) {
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if(constShift==1) {
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val opc = if(signed) Opcode.ASR else Opcode.LSR
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(opc, vmDt, reg1=loadReg)
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}
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} else {
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val shiftReg = codeGen.registers.next(IRDataType.BYTE)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=shiftReg, immediate=constShift and 255)
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val opc = if(signed) Opcode.ASRN else Opcode.LSRN
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it += IRInstruction(opc, vmDt, reg1=loadReg, reg2=shiftReg)
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}
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}
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} else {
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val shiftTr = exprGen.translateExpression(operand)
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addToResult(resultVar, shiftTr, shiftTr.resultReg, -1)
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resultVar += IRCodeChunk(null, null).also {
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val opc = if(signed) Opcode.ASRN else Opcode.LSRN
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it += IRInstruction(opc, vmDt, reg1=loadReg, reg2=shiftTr.resultReg)
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}
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}
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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return resultVar
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}
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if(constAddress==null && memory!=null)
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return null // TODO("optimized memory in-place >>"")
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val result = mutableListOf<IRCodeChunkBase>()
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if(codeGen.isOne(operand)) {
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@@ -2379,10 +2532,79 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val exprGen
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}
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return result
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}
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return null // TODO("optimized << in array")
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if(!array.splitWords) {
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val eltSize = codeGen.program.memsizer.memorySize(array.type, null)
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val resultVar = mutableListOf<IRCodeChunkBase>()
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val indexTr = exprGen.translateExpression(array.index)
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addToResult(resultVar, indexTr, indexTr.resultReg, -1)
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val (indexReg, indexDt) = normalizeArrayIndex(resultVar, indexTr)
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if(eltSize > 1)
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resultVar += codeGen.multiplyByConst(indexDt, indexReg, eltSize)
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val loadReg = codeGen.registers.next(vmDt)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADX, vmDt, reg1=loadReg, reg2=indexReg, labelSymbol=array.variable!!.name)
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}
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val constShift = operand.asConstInteger()
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if(constShift!=null) {
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if(constShift==1) {
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LSL, vmDt, reg1=loadReg)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1=loadReg, reg2=indexReg, labelSymbol=array.variable!!.name)
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}
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} else {
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val shiftReg = codeGen.registers.next(IRDataType.BYTE)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=shiftReg, immediate=constShift and 255)
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it += IRInstruction(Opcode.LSLN, vmDt, reg1=loadReg, reg2=shiftReg)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1=loadReg, reg2=indexReg, labelSymbol=array.variable!!.name)
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}
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}
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} else {
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val shiftTr = exprGen.translateExpression(operand)
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addToResult(resultVar, shiftTr, shiftTr.resultReg, -1)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LSLN, vmDt, reg1=loadReg, reg2=shiftTr.resultReg)
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it += IRInstruction(Opcode.STOREX, vmDt, reg1=loadReg, reg2=indexReg, labelSymbol=array.variable!!.name)
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}
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}
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return resultVar
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}
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return null
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}
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if(constAddress==null && memory!=null) {
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val resultVar = mutableListOf<IRCodeChunkBase>()
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val addrTr = exprGen.translateExpression(memory.address)
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addToResult(resultVar, addrTr, addrTr.resultReg, -1)
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val addressReg = addrTr.resultReg
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val loadReg = codeGen.registers.next(vmDt)
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val constShift = operand.asConstInteger()
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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if(constShift!=null) {
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if(constShift==1) {
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LSL, vmDt, reg1=loadReg)
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}
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} else {
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val shiftReg = codeGen.registers.next(IRDataType.BYTE)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, IRDataType.BYTE, reg1=shiftReg, immediate=constShift and 255)
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it += IRInstruction(Opcode.LSLN, vmDt, reg1=loadReg, reg2=shiftReg)
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}
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}
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} else {
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val shiftTr = exprGen.translateExpression(operand)
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addToResult(resultVar, shiftTr, shiftTr.resultReg, -1)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LSLN, vmDt, reg1=loadReg, reg2=shiftTr.resultReg)
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}
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}
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.STOREI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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return resultVar
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}
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if(constAddress==null && memory!=null)
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return null // TODO("optimized memory in-place <<"")
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val result = mutableListOf<IRCodeChunkBase>()
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if(codeGen.isOne(operand)){
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@@ -2603,7 +2825,7 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val exprGen
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return result
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}
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private fun operatorModuloInplace(symbol: String?, array: PtArrayIndexer?, constAddress: UInt?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks? {
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private fun operatorModuloInplace(symbol: String?, array: PtArrayIndexer?, constAddress: UInt?, memory: PtMemoryByte?, vmDt: IRDataType, operand: PtExpression, signed: Boolean): IRCodeChunks {
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if(array!=null) {
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if(array.splitWords)
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return operatorModuloInplaceSplitArray(array, operand, signed)
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@@ -2665,8 +2887,34 @@ internal class AssignmentGen(private val codeGen: IRCodeGen, private val exprGen
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}
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return result
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}
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if(constAddress==null && memory!=null)
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return null // TODO("optimized memory in-place %"")
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if(constAddress==null && memory!=null) {
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val resultVar = mutableListOf<IRCodeChunkBase>()
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val addrTr = exprGen.translateExpression(memory.address)
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addToResult(resultVar, addrTr, addrTr.resultReg, -1)
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val addressReg = addrTr.resultReg
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val loadReg = codeGen.registers.next(vmDt)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOADI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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val modROpcode = if(signed) Opcode.MODSR else Opcode.MODR
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val constVal = (operand as? PtNumber)?.number?.toInt()
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if(constVal!=null) {
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val constReg = codeGen.registers.next(vmDt)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, vmDt, reg1=constReg, immediate=constVal)
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it += IRInstruction(modROpcode, vmDt, reg1=loadReg, reg2=constReg)
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it += IRInstruction(Opcode.STOREI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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} else {
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val opTr = exprGen.translateExpression(operand)
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addToResult(resultVar, opTr, opTr.resultReg, -1)
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resultVar += IRCodeChunk(null, null).also {
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it += IRInstruction(modROpcode, vmDt, reg1=loadReg, reg2=opTr.resultReg)
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it += IRInstruction(Opcode.STOREI, vmDt, reg1=loadReg, reg2=addressReg, immediate=0)
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}
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}
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return resultVar
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}
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val result = mutableListOf<IRCodeChunkBase>()
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val resultReg = codeGen.registers.next(vmDt)
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