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vm: codegen uses INCM/DECM if possible
This commit is contained in:
Irmen de Jong
parent
517cf61d11
commit
a7df828932
@ -507,53 +507,53 @@ class CodeGen(internal val program: PtProgram,
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private fun translate(postIncrDecr: PtPostIncrDecr): VmCodeChunk {
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val code = VmCodeChunk()
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val operation = when(postIncrDecr.operator) {
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"++" -> Opcode.INC
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"--" -> Opcode.DEC
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val operationMem: Opcode
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val operationRegister: Opcode
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when(postIncrDecr.operator) {
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"++" -> {
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operationMem = Opcode.INCM
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operationRegister = Opcode.INC
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}
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"--" -> {
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operationMem = Opcode.DECM
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operationRegister = Opcode.DEC
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}
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else -> throw AssemblyError("weird operator")
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}
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val ident = postIncrDecr.target.identifier
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val memory = postIncrDecr.target.memory
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val array = postIncrDecr.target.array
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val vmDt = vmType(postIncrDecr.target.type)
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val resultReg = vmRegisters.nextFree()
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if(ident!=null) {
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val address = allocations.get(ident.targetName)
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code += VmCodeInstruction(Opcode.LOADM, vmDt, reg1=resultReg, value = address)
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code += VmCodeInstruction(operation, vmDt, reg1=resultReg)
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code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1=resultReg, value = address)
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code += VmCodeInstruction(operationMem, vmDt, value = address)
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} else if(memory!=null) {
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if(memory.address is PtNumber) {
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val address = (memory.address as PtNumber).number.toInt()
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code += VmCodeInstruction(Opcode.LOADM, vmDt, reg1 = resultReg, value = address)
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code += VmCodeInstruction(operation, vmDt, reg1 = resultReg)
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code += VmCodeInstruction(Opcode.STOREM, vmDt, reg1 = resultReg, value=address)
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code += VmCodeInstruction(operationMem, vmDt, value = address)
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} else {
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val incReg = vmRegisters.nextFree()
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val addressReg = vmRegisters.nextFree()
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code += expressionEval.translateExpression(memory.address, addressReg, -1)
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code += VmCodeInstruction(Opcode.LOADI, vmDt, reg1 = resultReg, reg2 = addressReg)
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code += VmCodeInstruction(operation, vmDt, reg1 = resultReg)
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code += VmCodeInstruction(Opcode.STOREI, vmDt, reg1 = resultReg, reg2 = addressReg)
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code += VmCodeInstruction(Opcode.LOADI, vmDt, reg1 = incReg, reg2 = addressReg)
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code += VmCodeInstruction(operationRegister, vmDt, reg1 = incReg)
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code += VmCodeInstruction(Opcode.STOREI, vmDt, reg1 = incReg, reg2 = addressReg)
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}
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} else if (array!=null) {
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val variable = array.variable.targetName
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var variableAddr = allocations.get(variable)
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val itemsize = program.memsizer.memorySize(array.type)
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val fixedIndex = constIntValue(array.index)
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val memOp = when(postIncrDecr.operator) {
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"++" -> Opcode.INCM
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"--" -> Opcode.DECM
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else -> throw AssemblyError("weird operator")
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}
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if(fixedIndex!=null) {
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variableAddr += fixedIndex*itemsize
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code += VmCodeInstruction(memOp, vmDt, value=variableAddr)
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code += VmCodeInstruction(operationMem, vmDt, value=variableAddr)
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} else {
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val incReg = vmRegisters.nextFree()
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val indexReg = vmRegisters.nextFree()
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code += expressionEval.translateExpression(array.index, indexReg, -1)
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code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=resultReg, reg2=indexReg, value=variableAddr)
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code += VmCodeInstruction(operation, vmDt, reg1=resultReg)
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code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1=resultReg, reg2=indexReg, value=variableAddr)
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code += VmCodeInstruction(Opcode.LOADX, vmDt, reg1=incReg, reg2=indexReg, value=variableAddr)
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code += VmCodeInstruction(operationRegister, vmDt, reg1=incReg)
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code += VmCodeInstruction(Opcode.STOREX, vmDt, reg1=incReg, reg2=indexReg, value=variableAddr)
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}
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} else
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throw AssemblyError("weird assigntarget")
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@ -173,7 +173,6 @@ internal class ExpressionGen(private val codeGen: CodeGen) {
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private fun translate(expr: PtPrefix, resultRegister: Int): VmCodeChunk {
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val code = VmCodeChunk()
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// TODO if the value is a variable or memory read, use memory-versions of the opcodes instead of using intermediary register
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code += translateExpression(expr.value, resultRegister, -1)
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val vmDt = codeGen.vmType(expr.type)
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when(expr.operator) {
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@ -3,7 +3,8 @@ TODO
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For next release
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^^^^^^^^^^^^^^^^
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- vm: use more instructions in codegen: branching
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- vm: use more instructions in codegen: branching, don't use the conditional set instructions here
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- vm: get rid of all the conditional set instructions
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- vm: add more instructions operating directly on memory instead of only registers?
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- in-place modifiying functions (rol, ror, ..) don't accept a memory address but require a memory-read expression. that is weird.
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- complete the Inliner
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@ -25,10 +25,24 @@ main {
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ubyte @shared value = inline_candidate()
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ubyte lowb = $31
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ubyte lowb = 4
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ubyte highb = $ea
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uword result = mkword(highb, lowb)
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txt.print_uwhex(result, true)
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if lowb==3
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lowb++
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if lowb!=3
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lowb++
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if lowb==3
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lowb++
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else
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lowb--
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if lowb!=3
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lowb++
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else
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lowb--
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; txt.print_ub(inline_candidate())
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; txt.nl()
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@ -184,8 +184,8 @@ enum class Opcode {
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BSTPOS,
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BZ,
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BNZ,
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BEQ,
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BNE,
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BEQ, // TODO not used in codegen??? == nonzero
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BNE, // TODO not used in codegen??? != nonzero
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BLT, // TODO not used in codegen??? <
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BLTS, // TODO not used in codegen??? <
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BGT, // TODO not used in codegen??? >
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