fix register stack saving on certain expression code that was broken on 6502 but not on 65c02

This commit is contained in:
Irmen de Jong 2023-08-29 11:50:35 +02:00
parent 2d7ebff8e9
commit aa4d23a3d5
3 changed files with 52 additions and 5 deletions

View File

@ -163,7 +163,7 @@ internal class AugmentableAssignmentAsmGen(private val program: PtProgram,
else -> {
asmgen.assignExpressionTo(memory.address, AsmAssignTarget(TargetStorageKind.REGISTER, asmgen, DataType.UWORD, memory.definingISub(), target.position, register = RegisterOrPair.AY))
asmgen.saveRegisterStack(CpuRegister.A, true)
asmgen.saveRegisterStack(CpuRegister.Y, false)
asmgen.saveRegisterStack(CpuRegister.Y, true)
asmgen.out(" jsr prog8_lib.read_byte_from_address_in_AY_into_A")
when(value.kind) {
SourceStorageKind.LITERALNUMBER -> {

View File

@ -1,7 +1,5 @@
TODO
====
- maze example is broken on c64/c128 (not on cx16...)
- prefix prog8 subroutines with p8s_ instead of p8_ to not let them clash with variables in the asm?
- allow 'chained' array indexing for expressions: value = ptrarray[0][0]

View File

@ -14,6 +14,7 @@ main {
maze.initialize()
maze.drawStartFinish()
maze.generate()
maze.openpassages()
maze.drawStartFinish()
maze.solve()
maze.drawStartFinish()
@ -66,6 +67,8 @@ maze {
}
}
ubyte[4] directionflags = [LEFT,RIGHT,UP,DOWN]
sub generate() {
ubyte cx = startCx
ubyte cy = startCy
@ -163,15 +166,61 @@ carve_restart_after_repath:
if not candidates
return 0
ubyte[4] bitflags = [LEFT,RIGHT,UP,DOWN]
repeat {
ubyte choice = candidates & bitflags[math.rnd() & 3]
ubyte choice = candidates & directionflags[math.rnd() & 3]
if choice
return choice
}
}
}
sub openpassages() {
; open just a few extra passages, so that multiple routes are possible in theory.
ubyte cell
ubyte numpassages
ubyte cx
ubyte cy
do {
do {
cx = math.rnd() % (numCellsHoriz-2) + 1
cy = math.rnd() % (numCellsVert-2) + 1
} until not @(celladdr(cx, cy)) & STONE
ubyte direction = directionflags[math.rnd() & 3]
if not @(celladdr(cx, cy)) & direction {
when direction {
LEFT -> {
if not @(celladdr(cx-1,cy)) & STONE {
@(celladdr(cx,cy)) |= LEFT
drawCell(cx,cy)
numpassages++
}
}
RIGHT -> {
if not @(celladdr(cx+1,cy)) & STONE {
@(celladdr(cx,cy)) |= RIGHT
drawCell(cx,cy)
numpassages++
}
}
UP -> {
if not @(celladdr(cx,cy-1)) & STONE {
@(celladdr(cx,cy)) |= UP
drawCell(cx,cy)
numpassages++
}
}
DOWN -> {
if not @(celladdr(cx,cy+1)) & STONE {
@(celladdr(cx,cy)) |= DOWN
drawCell(cx,cy)
numpassages++
}
}
}
}
} until numpassages==10
}
sub solve() {
ubyte cx = startCx
ubyte cy = startCy