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https://github.com/irmen/prog8.git
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IR: fix codegen for routines returning in CPU Status register flag
This commit is contained in:
Irmen de Jong
parent
332ba8ed7e
commit
b24df31c2b
@ -430,6 +430,7 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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result += tr.chunks
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}
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// return value
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var statusFlagResult: Statusflag? = null
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val returnRegSpec = if(fcall.void) null else {
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if(callTarget.returns.isEmpty())
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null
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@ -438,8 +439,11 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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val returnIrType = irType(returns.type)
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if(returnIrType==IRDataType.FLOAT)
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FunctionCallArgs.RegSpec(returnIrType, codeGen.registers.nextFreeFloat(), returns.register)
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else
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FunctionCallArgs.RegSpec(returnIrType, codeGen.registers.nextFree(), returns.register)
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else {
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statusFlagResult = returns.register.statusflag
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val returnRegister = if(statusFlagResult==null) codeGen.registers.nextFree() else -1
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FunctionCallArgs.RegSpec(returnIrType, returnRegister, returns.register)
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}
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} else {
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// multiple return values: take the first *register* (not status flag) return value and ignore the rest.
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val returns = callTarget.returns.first { it.register.registerOrPair!=null }
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@ -457,12 +461,49 @@ internal class ExpressionGen(private val codeGen: IRCodeGen) {
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else
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IRInstruction(Opcode.CALL, address = callTarget.address!!.toInt(), fcallArgs = FunctionCallArgs(argRegisters, returnRegSpec))
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addInstr(result, call, null)
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var finalReturnRegister = returnRegSpec?.registerNum ?: -1
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if(fcall.parent is PtAssignment) {
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// look if the status flag bit should actually be returned as a 0/1 byte value in a result register (so it can be assigned)
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if(statusFlagResult!=null && returnRegSpec!=null) {
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// assign status flag bit to the return value register
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finalReturnRegister = codeGen.registers.nextFree()
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when(statusFlagResult) {
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Statusflag.Pc -> {
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(Opcode.LOAD, returnRegSpec.dt, reg1=finalReturnRegister, immediate = 0)
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it += IRInstruction(Opcode.ROXL, returnRegSpec.dt, reg1=finalReturnRegister)
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}
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}
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else -> {
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val branchOpcode = when(statusFlagResult) {
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Statusflag.Pc -> Opcode.BSTCS
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Statusflag.Pz -> Opcode.BSTEQ
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Statusflag.Pv -> Opcode.BSTVS
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Statusflag.Pn -> Opcode.BSTNEG
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}
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val setLabel = codeGen.createLabelName()
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val endLabel = codeGen.createLabelName()
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result += IRCodeChunk(null, null).also {
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it += IRInstruction(branchOpcode, labelSymbol = setLabel)
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it += IRInstruction(Opcode.LOAD, returnRegSpec.dt, reg1=finalReturnRegister, immediate = 0)
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it += IRInstruction(Opcode.JUMP, labelSymbol = endLabel)
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}
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result += IRCodeChunk(setLabel, null).also {
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it += IRInstruction(Opcode.LOAD, returnRegSpec.dt, reg1=finalReturnRegister, immediate = 1)
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}
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result += IRCodeChunk(endLabel, null)
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}
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}
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}
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}
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return if(fcall.void)
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ExpressionCodeResult(result, IRDataType.BYTE, -1, -1)
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else if(fcall.type==DataType.FLOAT)
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ExpressionCodeResult(result, returnRegSpec!!.dt, -1, returnRegSpec.registerNum)
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ExpressionCodeResult(result, returnRegSpec!!.dt, -1, finalReturnRegister)
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else
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ExpressionCodeResult(result, returnRegSpec!!.dt, returnRegSpec.registerNum, -1)
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ExpressionCodeResult(result, returnRegSpec!!.dt, finalReturnRegister, -1)
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}
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else -> throw AssemblyError("invalid node type")
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}
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@ -2,8 +2,6 @@
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TODO
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====
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- IR (expericodegen): fix code for calling routines that return a boolean in a status register such as Carry flag, it has to store the flag value somewhere
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- merge branch optimize-st for some optimizations regarding SymbolTable use
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- [on branch: call-pointers] allow calling a subroutine via a pointer variable (indirect JSR, optimized form of callfar())
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@ -18,6 +16,8 @@ Future Things and Ideas
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^^^^^^^^^^^^^^^^^^^^^^^
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Compiler:
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- What happens when subs return a boolean not in A, but in Carry flag?
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- What happens when we keep the BOOL type around until in codegen? (so, get rid of Boolean->ubyte and boolean remover)
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- Multidimensional arrays and chained indexing, purely as syntactic sugar over regular arrays.
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- make a form of "manual generics" possible like: varsub routine(T arg)->T where T is expanded to a specific type
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(this is already done hardcoded for several of the builtin functions)
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@ -4,54 +4,33 @@
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main {
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sub start() {
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if test_c_set()
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txt.print("yes1\n")
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else
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goto skip1
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bool @shared statusc = test_carry_set()
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bool @shared statusv = test_v_set()
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bool @shared statusz = test_z_set()
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bool @shared statusn = test_n_set()
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txt.print("no1\n")
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skip1:
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if test_c_clear()
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txt.print("yes2\n")
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else
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goto skip2
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txt.print("no1\n")
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skip2:
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txt.print("done\n")
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if test_carry_set() {
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txt.print("set!\n")
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}
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if test_v_set() {
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txt.print("set!\n")
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}
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if test_z_set() {
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txt.print("set!\n")
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}
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if test_n_set() {
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txt.print("set!\n")
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}
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}
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asmsub test_c_clear() -> bool @Pc {
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asmsub test_carry_set() -> bool @Pc {
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%asm {{
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clc
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sec
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rts
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}}
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}
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asmsub test_z_clear() -> bool @Pz {
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%asm {{
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lda #1
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rts
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}}
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}
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asmsub test_n_clear() -> bool @Pn {
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%asm {{
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lda #1
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rts
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}}
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}
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asmsub test_v_clear() -> bool @Pv {
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%asm {{
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clv
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rts
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}}
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}
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asmsub test_c_set() -> bool @Pc {
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asmsub test_v_set() -> bool @Pv {
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%asm {{
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sec
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rts
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@ -60,22 +39,15 @@ skip2:
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asmsub test_z_set() -> bool @Pz {
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%asm {{
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lda #0
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sec
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rts
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}}
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}
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asmsub test_n_set() -> bool @Pn {
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%asm {{
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lda #-1
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sec
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rts
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}}
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}
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asmsub test_v_set() -> bool @Pv {
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%asm {{
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bit +
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+ rts
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}}
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}
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}
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@ -928,18 +928,27 @@ data class IRInstruction(
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val returns = fcallArgs.returns
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if(returns!=null) {
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result.add(":")
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when (returns.dt) {
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IRDataType.BYTE -> result.add("r${returns.registerNum}.b")
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IRDataType.WORD -> result.add("r${returns.registerNum}.w")
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IRDataType.FLOAT -> result.add("fr${returns.registerNum}.f")
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val cpuReg = if(returns.cpuRegister==null) "" else {
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if(returns.cpuRegister.registerOrPair!=null)
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returns.cpuRegister.registerOrPair.toString()
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else
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returns.cpuRegister.statusflag.toString()
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}
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if(returns.cpuRegister!=null) {
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val cpuReg =
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if(returns.cpuRegister.registerOrPair!=null)
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returns.cpuRegister.registerOrPair.toString()
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else
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returns.cpuRegister.statusflag.toString()
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result.add("@"+cpuReg)
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if(cpuReg.isEmpty()) {
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when (returns.dt) {
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IRDataType.BYTE -> result.add("r${returns.registerNum}.b")
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IRDataType.WORD -> result.add("r${returns.registerNum}.w")
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IRDataType.FLOAT -> result.add("fr${returns.registerNum}.f")
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}
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} else {
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result.add("@" + cpuReg)
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if(returns.cpuRegister?.statusflag==null) {
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when (returns.dt) {
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IRDataType.BYTE -> result.add(".b")
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IRDataType.WORD -> result.add(".w")
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IRDataType.FLOAT -> result.add(".f")
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}
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}
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}
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}
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} else {
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@ -254,6 +254,14 @@ private fun parseCall(rest: String): ParsedCall {
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return FunctionCallArgs.RegSpec(type, num, cpuRegister)
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}
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fun parseReturnRegspec(reg: String): FunctionCallArgs.RegSpec {
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return if(reg.startsWith('@')) {
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FunctionCallArgs.RegSpec(IRDataType.BYTE, -1, parseRegisterOrStatusflag(reg.drop(1)))
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} else {
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parseRegspec(reg)
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}
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}
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fun parseArgs(args: String): List<FunctionCallArgs.ArgumentSpec> {
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if(args.isBlank())
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return emptyList()
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@ -285,7 +293,7 @@ private fun parseCall(rest: String): ParsedCall {
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actualTarget,
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address,
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arguments,
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if(returns==null) null else parseRegspec(returns)
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if(returns==null) null else parseReturnRegspec(returns)
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)
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}
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