From b4000104260b68d672d8ec36e0a97ef27b064292 Mon Sep 17 00:00:00 2001 From: Irmen de Jong Date: Sun, 8 Sep 2019 19:11:06 +0200 Subject: [PATCH] separated the 6502 test suite into separate unit tests --- sim65/build.gradle | 5 +- sim65/src/C64KernalStubs.kt | 47 - sim65/src/Sim65Main.kt | 86 +- sim65/src/Sim65MainBCDtest.kt | 89 -- sim65/src/components/Cpu6502.kt | 4 +- {c64tests => sim65/test/6502testsuite}/0start | Bin .../test/6502testsuite}/_Test Suite 2.15.txt | 0 {c64tests => sim65/test/6502testsuite}/adca | Bin {c64tests => sim65/test/6502testsuite}/adcax | Bin {c64tests => sim65/test/6502testsuite}/adcay | Bin {c64tests => sim65/test/6502testsuite}/adcb | Bin {c64tests => sim65/test/6502testsuite}/adcix | Bin {c64tests => sim65/test/6502testsuite}/adciy | Bin {c64tests => sim65/test/6502testsuite}/adcz | Bin {c64tests => sim65/test/6502testsuite}/adczx | Bin {c64tests => sim65/test/6502testsuite}/alrb | Bin {c64tests => sim65/test/6502testsuite}/ancb | Bin {c64tests => sim65/test/6502testsuite}/anda | Bin {c64tests => sim65/test/6502testsuite}/andax | Bin {c64tests => sim65/test/6502testsuite}/anday | Bin {c64tests => sim65/test/6502testsuite}/andb | Bin {c64tests => sim65/test/6502testsuite}/andix | Bin {c64tests => sim65/test/6502testsuite}/andiy | Bin {c64tests => sim65/test/6502testsuite}/andz | Bin {c64tests => sim65/test/6502testsuite}/andzx | Bin {c64tests => sim65/test/6502testsuite}/aneb | Bin {c64tests => sim65/test/6502testsuite}/arrb | Bin {c64tests => sim65/test/6502testsuite}/asla | Bin {c64tests => sim65/test/6502testsuite}/aslax | Bin {c64tests => sim65/test/6502testsuite}/asln | Bin {c64tests => sim65/test/6502testsuite}/aslz | Bin {c64tests => sim65/test/6502testsuite}/aslzx | Bin {c64tests => sim65/test/6502testsuite}/asoa | Bin {c64tests => sim65/test/6502testsuite}/asoax | Bin {c64tests => sim65/test/6502testsuite}/asoay | Bin {c64tests => sim65/test/6502testsuite}/asoix | Bin {c64tests => sim65/test/6502testsuite}/asoiy | Bin {c64tests => sim65/test/6502testsuite}/asoz | Bin {c64tests => sim65/test/6502testsuite}/asozx | Bin {c64tests => sim65/test/6502testsuite}/axsa | Bin {c64tests => sim65/test/6502testsuite}/axsix | Bin {c64tests => sim65/test/6502testsuite}/axsz | Bin {c64tests => sim65/test/6502testsuite}/axszy | Bin {c64tests => sim65/test/6502testsuite}/bccr | Bin {c64tests => sim65/test/6502testsuite}/bcsr | Bin {c64tests => sim65/test/6502testsuite}/beqr | Bin {c64tests => sim65/test/6502testsuite}/bita | Bin {c64tests => sim65/test/6502testsuite}/bitz | Bin {c64tests => sim65/test/6502testsuite}/bmir | Bin {c64tests => sim65/test/6502testsuite}/bner | Bin {c64tests => sim65/test/6502testsuite}/bplr | Bin .../test/6502testsuite}/branchwrap | Bin {c64tests => sim65/test/6502testsuite}/brkn | Bin {c64tests => sim65/test/6502testsuite}/bvcr | Bin {c64tests => sim65/test/6502testsuite}/bvsr | Bin .../test/6502testsuite}/cia1pb6 | Bin .../test/6502testsuite}/cia1pb7 | Bin {c64tests => sim65/test/6502testsuite}/cia1ta | Bin .../test/6502testsuite}/cia1tab | Bin {c64tests => sim65/test/6502testsuite}/cia1tb | Bin .../test/6502testsuite}/cia1tb123 | Bin .../test/6502testsuite}/cia2pb6 | Bin .../test/6502testsuite}/cia2pb7 | Bin {c64tests => sim65/test/6502testsuite}/cia2ta | Bin {c64tests => sim65/test/6502testsuite}/cia2tb | Bin .../test/6502testsuite}/cia2tb123 | Bin {c64tests => sim65/test/6502testsuite}/clcn | Bin {c64tests => sim65/test/6502testsuite}/cldn | Bin {c64tests => sim65/test/6502testsuite}/clin | Bin {c64tests => sim65/test/6502testsuite}/clvn | Bin {c64tests => sim65/test/6502testsuite}/cmpa | Bin {c64tests => sim65/test/6502testsuite}/cmpax | Bin {c64tests => sim65/test/6502testsuite}/cmpay | Bin {c64tests => sim65/test/6502testsuite}/cmpb | Bin {c64tests => sim65/test/6502testsuite}/cmpix | Bin {c64tests => sim65/test/6502testsuite}/cmpiy | Bin {c64tests => sim65/test/6502testsuite}/cmpz | Bin {c64tests => sim65/test/6502testsuite}/cmpzx | Bin {c64tests => sim65/test/6502testsuite}/cntdef | Bin {c64tests => sim65/test/6502testsuite}/cnto2 | Bin .../test/6502testsuite}/cpuport | Bin .../test/6502testsuite}/cputiming | Bin {c64tests => sim65/test/6502testsuite}/cpxa | Bin {c64tests => sim65/test/6502testsuite}/cpxb | Bin {c64tests => sim65/test/6502testsuite}/cpxz | Bin {c64tests => sim65/test/6502testsuite}/cpya | Bin {c64tests => sim65/test/6502testsuite}/cpyb | Bin {c64tests => sim65/test/6502testsuite}/cpyz | Bin {c64tests => sim65/test/6502testsuite}/dcma | Bin {c64tests => sim65/test/6502testsuite}/dcmax | Bin {c64tests => sim65/test/6502testsuite}/dcmay | Bin {c64tests => sim65/test/6502testsuite}/dcmix | Bin {c64tests => sim65/test/6502testsuite}/dcmiy | Bin {c64tests => sim65/test/6502testsuite}/dcmz | Bin {c64tests => sim65/test/6502testsuite}/dcmzx | Bin {c64tests => sim65/test/6502testsuite}/deca | Bin {c64tests => sim65/test/6502testsuite}/decax | Bin {c64tests => sim65/test/6502testsuite}/decz | Bin {c64tests => sim65/test/6502testsuite}/deczx | Bin {c64tests => sim65/test/6502testsuite}/dexn | Bin {c64tests => sim65/test/6502testsuite}/deyn | Bin {c64tests => sim65/test/6502testsuite}/eora | Bin {c64tests => sim65/test/6502testsuite}/eorax | Bin {c64tests => sim65/test/6502testsuite}/eoray | Bin {c64tests => sim65/test/6502testsuite}/eorb | Bin {c64tests => sim65/test/6502testsuite}/eorix | Bin {c64tests => sim65/test/6502testsuite}/eoriy | Bin {c64tests => sim65/test/6502testsuite}/eorz | Bin {c64tests => sim65/test/6502testsuite}/eorzx | Bin {c64tests => sim65/test/6502testsuite}/finish | Bin {c64tests => sim65/test/6502testsuite}/flipos | Bin {c64tests => sim65/test/6502testsuite}/icr01 | Bin {c64tests => sim65/test/6502testsuite}/imr | Bin {c64tests => sim65/test/6502testsuite}/inca | Bin {c64tests => sim65/test/6502testsuite}/incax | Bin {c64tests => sim65/test/6502testsuite}/incz | Bin {c64tests => sim65/test/6502testsuite}/inczx | Bin {c64tests => sim65/test/6502testsuite}/insa | Bin {c64tests => sim65/test/6502testsuite}/insax | Bin {c64tests => sim65/test/6502testsuite}/insay | Bin {c64tests => sim65/test/6502testsuite}/insix | Bin {c64tests => sim65/test/6502testsuite}/insiy | Bin {c64tests => sim65/test/6502testsuite}/insz | Bin {c64tests => sim65/test/6502testsuite}/inszx | Bin {c64tests => sim65/test/6502testsuite}/inxn | Bin {c64tests => sim65/test/6502testsuite}/inyn | Bin {c64tests => sim65/test/6502testsuite}/irq | Bin {c64tests => sim65/test/6502testsuite}/jmpi | Bin {c64tests => sim65/test/6502testsuite}/jmpw | Bin {c64tests => sim65/test/6502testsuite}/jsrw | Bin {c64tests => sim65/test/6502testsuite}/lasay | Bin {c64tests => sim65/test/6502testsuite}/laxa | Bin {c64tests => sim65/test/6502testsuite}/laxay | Bin {c64tests => sim65/test/6502testsuite}/laxix | Bin {c64tests => sim65/test/6502testsuite}/laxiy | Bin {c64tests => sim65/test/6502testsuite}/laxz | Bin {c64tests => sim65/test/6502testsuite}/laxzy | Bin {c64tests => sim65/test/6502testsuite}/ldaa | Bin {c64tests => sim65/test/6502testsuite}/ldaax | Bin {c64tests => sim65/test/6502testsuite}/ldaay | Bin {c64tests => sim65/test/6502testsuite}/ldab | Bin {c64tests => sim65/test/6502testsuite}/ldaix | Bin {c64tests => sim65/test/6502testsuite}/ldaiy | Bin {c64tests => sim65/test/6502testsuite}/ldaz | Bin {c64tests => sim65/test/6502testsuite}/ldazx | Bin {c64tests => sim65/test/6502testsuite}/ldxa | Bin {c64tests => sim65/test/6502testsuite}/ldxay | Bin {c64tests => sim65/test/6502testsuite}/ldxb | Bin {c64tests => sim65/test/6502testsuite}/ldxz | Bin {c64tests => sim65/test/6502testsuite}/ldxzy | Bin {c64tests => sim65/test/6502testsuite}/ldya | Bin {c64tests => sim65/test/6502testsuite}/ldyax | Bin {c64tests => sim65/test/6502testsuite}/ldyb | Bin {c64tests => sim65/test/6502testsuite}/ldyz | Bin {c64tests => sim65/test/6502testsuite}/ldyzx | Bin {c64tests => sim65/test/6502testsuite}/loadth | Bin {c64tests => sim65/test/6502testsuite}/lsea | Bin {c64tests => sim65/test/6502testsuite}/lseax | Bin {c64tests => sim65/test/6502testsuite}/lseay | Bin {c64tests => sim65/test/6502testsuite}/lseix | Bin {c64tests => sim65/test/6502testsuite}/lseiy | Bin {c64tests => sim65/test/6502testsuite}/lsez | Bin {c64tests => sim65/test/6502testsuite}/lsezx | Bin {c64tests => sim65/test/6502testsuite}/lsra | Bin {c64tests => sim65/test/6502testsuite}/lsrax | Bin {c64tests => sim65/test/6502testsuite}/lsrn | Bin {c64tests => sim65/test/6502testsuite}/lsrz | Bin {c64tests => sim65/test/6502testsuite}/lsrzx | Bin {c64tests => sim65/test/6502testsuite}/lxab | Bin {c64tests => sim65/test/6502testsuite}/mmu | Bin .../test/6502testsuite}/mmufetch | Bin {c64tests => sim65/test/6502testsuite}/nmi | Bin {c64tests => sim65/test/6502testsuite}/nopa | Bin {c64tests => sim65/test/6502testsuite}/nopax | Bin {c64tests => sim65/test/6502testsuite}/nopb | Bin {c64tests => sim65/test/6502testsuite}/nopn | Bin {c64tests => sim65/test/6502testsuite}/nopz | Bin {c64tests => sim65/test/6502testsuite}/nopzx | Bin .../test/6502testsuite}/oneshot | Bin {c64tests => sim65/test/6502testsuite}/oraa | Bin {c64tests => sim65/test/6502testsuite}/oraax | Bin {c64tests => sim65/test/6502testsuite}/oraay | Bin {c64tests => sim65/test/6502testsuite}/orab | Bin {c64tests => sim65/test/6502testsuite}/oraix | Bin {c64tests => sim65/test/6502testsuite}/oraiy | Bin {c64tests => sim65/test/6502testsuite}/oraz | Bin {c64tests => sim65/test/6502testsuite}/orazx | Bin {c64tests => sim65/test/6502testsuite}/phan | Bin {c64tests => sim65/test/6502testsuite}/phpn | Bin {c64tests => sim65/test/6502testsuite}/plan | Bin {c64tests => sim65/test/6502testsuite}/plpn | Bin {c64tests => sim65/test/6502testsuite}/rlaa | Bin {c64tests => sim65/test/6502testsuite}/rlaax | Bin {c64tests => sim65/test/6502testsuite}/rlaay | Bin {c64tests => sim65/test/6502testsuite}/rlaix | Bin {c64tests => sim65/test/6502testsuite}/rlaiy | Bin {c64tests => sim65/test/6502testsuite}/rlaz | Bin {c64tests => sim65/test/6502testsuite}/rlazx | Bin {c64tests => sim65/test/6502testsuite}/rola | Bin {c64tests => sim65/test/6502testsuite}/rolax | Bin {c64tests => sim65/test/6502testsuite}/roln | Bin {c64tests => sim65/test/6502testsuite}/rolz | Bin {c64tests => sim65/test/6502testsuite}/rolzx | Bin {c64tests => sim65/test/6502testsuite}/rora | Bin {c64tests => sim65/test/6502testsuite}/rorax | Bin {c64tests => sim65/test/6502testsuite}/rorn | Bin {c64tests => sim65/test/6502testsuite}/rorz | Bin {c64tests => sim65/test/6502testsuite}/rorzx | Bin {c64tests => sim65/test/6502testsuite}/rraa | Bin {c64tests => sim65/test/6502testsuite}/rraax | Bin {c64tests => sim65/test/6502testsuite}/rraay | Bin {c64tests => sim65/test/6502testsuite}/rraix | Bin {c64tests => sim65/test/6502testsuite}/rraiy | Bin {c64tests => sim65/test/6502testsuite}/rraz | Bin {c64tests => sim65/test/6502testsuite}/rrazx | Bin {c64tests => sim65/test/6502testsuite}/rtin | Bin {c64tests => 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sim65/test/6502testsuite}/staax | Bin {c64tests => sim65/test/6502testsuite}/staay | Bin {c64tests => sim65/test/6502testsuite}/staix | Bin {c64tests => sim65/test/6502testsuite}/staiy | Bin {c64tests => sim65/test/6502testsuite}/staz | Bin {c64tests => sim65/test/6502testsuite}/stazx | Bin {c64tests => sim65/test/6502testsuite}/stxa | Bin {c64tests => sim65/test/6502testsuite}/stxz | Bin {c64tests => sim65/test/6502testsuite}/stxzy | Bin {c64tests => sim65/test/6502testsuite}/stya | Bin {c64tests => sim65/test/6502testsuite}/styz | Bin {c64tests => sim65/test/6502testsuite}/styzx | Bin {c64tests => sim65/test/6502testsuite}/taxn | Bin {c64tests => sim65/test/6502testsuite}/tayn | Bin {c64tests => sim65/test/6502testsuite}/trap1 | Bin {c64tests => sim65/test/6502testsuite}/trap10 | Bin {c64tests => sim65/test/6502testsuite}/trap11 | Bin {c64tests => sim65/test/6502testsuite}/trap12 | Bin {c64tests => sim65/test/6502testsuite}/trap13 | Bin {c64tests => sim65/test/6502testsuite}/trap14 | Bin {c64tests => sim65/test/6502testsuite}/trap15 | Bin {c64tests => sim65/test/6502testsuite}/trap16 | Bin {c64tests => sim65/test/6502testsuite}/trap17 | Bin {c64tests => sim65/test/6502testsuite}/trap2 | Bin {c64tests => sim65/test/6502testsuite}/trap3 | Bin {c64tests => sim65/test/6502testsuite}/trap4 | Bin {c64tests => sim65/test/6502testsuite}/trap5 | Bin {c64tests => sim65/test/6502testsuite}/trap6 | Bin {c64tests => sim65/test/6502testsuite}/trap7 | Bin {c64tests => sim65/test/6502testsuite}/trap8 | Bin {c64tests => sim65/test/6502testsuite}/trap9 | Bin {c64tests => sim65/test/6502testsuite}/tsxn | Bin {c64tests => sim65/test/6502testsuite}/txan | Bin {c64tests => sim65/test/6502testsuite}/txsn | Bin {c64tests => sim65/test/6502testsuite}/tyan | Bin sim65/test/C64KernalStubs.kt | 49 + sim65/test/Test6502.kt | 2 +- sim65/test/Test6502TestSuite.kt | 1382 +++++++++++++++++ sim65/test/TestCommon6502.kt | 14 +- 275 files changed, 1501 insertions(+), 177 deletions(-) delete mode 100644 sim65/src/C64KernalStubs.kt delete mode 100644 sim65/src/Sim65MainBCDtest.kt rename {c64tests => sim65/test/6502testsuite}/0start (100%) rename {c64tests => sim65/test/6502testsuite}/_Test Suite 2.15.txt (100%) rename {c64tests => sim65/test/6502testsuite}/adca (100%) rename {c64tests => sim65/test/6502testsuite}/adcax (100%) rename {c64tests => sim65/test/6502testsuite}/adcay (100%) rename {c64tests => sim65/test/6502testsuite}/adcb (100%) rename {c64tests => sim65/test/6502testsuite}/adcix (100%) rename {c64tests => sim65/test/6502testsuite}/adciy (100%) rename {c64tests => sim65/test/6502testsuite}/adcz (100%) rename {c64tests => sim65/test/6502testsuite}/adczx (100%) rename {c64tests => sim65/test/6502testsuite}/alrb (100%) rename {c64tests => sim65/test/6502testsuite}/ancb (100%) rename {c64tests => sim65/test/6502testsuite}/anda (100%) rename {c64tests => sim65/test/6502testsuite}/andax (100%) rename {c64tests => sim65/test/6502testsuite}/anday (100%) rename {c64tests => sim65/test/6502testsuite}/andb (100%) rename {c64tests => sim65/test/6502testsuite}/andix (100%) rename {c64tests => sim65/test/6502testsuite}/andiy (100%) rename {c64tests => sim65/test/6502testsuite}/andz (100%) rename {c64tests => sim65/test/6502testsuite}/andzx (100%) rename {c64tests => sim65/test/6502testsuite}/aneb (100%) rename {c64tests => sim65/test/6502testsuite}/arrb (100%) rename {c64tests => sim65/test/6502testsuite}/asla (100%) rename {c64tests => sim65/test/6502testsuite}/aslax (100%) rename {c64tests => sim65/test/6502testsuite}/asln (100%) rename {c64tests => sim65/test/6502testsuite}/aslz (100%) rename {c64tests => sim65/test/6502testsuite}/aslzx (100%) rename {c64tests => sim65/test/6502testsuite}/asoa (100%) rename {c64tests => sim65/test/6502testsuite}/asoax (100%) rename {c64tests => sim65/test/6502testsuite}/asoay (100%) rename {c64tests => sim65/test/6502testsuite}/asoix (100%) rename {c64tests => sim65/test/6502testsuite}/asoiy (100%) rename {c64tests => sim65/test/6502testsuite}/asoz (100%) rename {c64tests => sim65/test/6502testsuite}/asozx (100%) rename {c64tests => sim65/test/6502testsuite}/axsa (100%) rename {c64tests => sim65/test/6502testsuite}/axsix (100%) rename {c64tests => sim65/test/6502testsuite}/axsz (100%) rename {c64tests => sim65/test/6502testsuite}/axszy (100%) rename {c64tests => sim65/test/6502testsuite}/bccr (100%) rename {c64tests => sim65/test/6502testsuite}/bcsr (100%) rename {c64tests => sim65/test/6502testsuite}/beqr (100%) rename {c64tests => sim65/test/6502testsuite}/bita (100%) rename {c64tests => sim65/test/6502testsuite}/bitz (100%) rename {c64tests => sim65/test/6502testsuite}/bmir (100%) rename {c64tests => sim65/test/6502testsuite}/bner (100%) rename {c64tests => sim65/test/6502testsuite}/bplr (100%) rename {c64tests => sim65/test/6502testsuite}/branchwrap (100%) rename {c64tests => sim65/test/6502testsuite}/brkn (100%) rename {c64tests => sim65/test/6502testsuite}/bvcr (100%) rename {c64tests => sim65/test/6502testsuite}/bvsr (100%) rename {c64tests => sim65/test/6502testsuite}/cia1pb6 (100%) rename {c64tests => sim65/test/6502testsuite}/cia1pb7 (100%) rename {c64tests => sim65/test/6502testsuite}/cia1ta (100%) rename {c64tests => sim65/test/6502testsuite}/cia1tab (100%) rename {c64tests => sim65/test/6502testsuite}/cia1tb (100%) rename {c64tests => sim65/test/6502testsuite}/cia1tb123 (100%) rename {c64tests => sim65/test/6502testsuite}/cia2pb6 (100%) rename {c64tests => sim65/test/6502testsuite}/cia2pb7 (100%) rename {c64tests => sim65/test/6502testsuite}/cia2ta (100%) rename {c64tests => sim65/test/6502testsuite}/cia2tb (100%) rename {c64tests => sim65/test/6502testsuite}/cia2tb123 (100%) rename {c64tests => sim65/test/6502testsuite}/clcn (100%) rename {c64tests => sim65/test/6502testsuite}/cldn (100%) rename {c64tests => sim65/test/6502testsuite}/clin (100%) rename {c64tests => sim65/test/6502testsuite}/clvn (100%) rename {c64tests => sim65/test/6502testsuite}/cmpa (100%) rename {c64tests => sim65/test/6502testsuite}/cmpax (100%) rename {c64tests => sim65/test/6502testsuite}/cmpay (100%) rename {c64tests => sim65/test/6502testsuite}/cmpb (100%) rename {c64tests => sim65/test/6502testsuite}/cmpix (100%) rename {c64tests => sim65/test/6502testsuite}/cmpiy (100%) rename {c64tests => sim65/test/6502testsuite}/cmpz (100%) rename {c64tests => sim65/test/6502testsuite}/cmpzx (100%) rename {c64tests => sim65/test/6502testsuite}/cntdef (100%) rename {c64tests => sim65/test/6502testsuite}/cnto2 (100%) rename {c64tests => sim65/test/6502testsuite}/cpuport (100%) rename {c64tests => sim65/test/6502testsuite}/cputiming (100%) rename {c64tests => sim65/test/6502testsuite}/cpxa (100%) rename {c64tests => sim65/test/6502testsuite}/cpxb (100%) rename {c64tests => sim65/test/6502testsuite}/cpxz (100%) rename {c64tests => sim65/test/6502testsuite}/cpya (100%) rename {c64tests => sim65/test/6502testsuite}/cpyb (100%) rename {c64tests => sim65/test/6502testsuite}/cpyz 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rename {c64tests => sim65/test/6502testsuite}/trap17 (100%) rename {c64tests => sim65/test/6502testsuite}/trap2 (100%) rename {c64tests => sim65/test/6502testsuite}/trap3 (100%) rename {c64tests => sim65/test/6502testsuite}/trap4 (100%) rename {c64tests => sim65/test/6502testsuite}/trap5 (100%) rename {c64tests => sim65/test/6502testsuite}/trap6 (100%) rename {c64tests => sim65/test/6502testsuite}/trap7 (100%) rename {c64tests => sim65/test/6502testsuite}/trap8 (100%) rename {c64tests => sim65/test/6502testsuite}/trap9 (100%) rename {c64tests => sim65/test/6502testsuite}/tsxn (100%) rename {c64tests => sim65/test/6502testsuite}/txan (100%) rename {c64tests => sim65/test/6502testsuite}/txsn (100%) rename {c64tests => sim65/test/6502testsuite}/tyan (100%) create mode 100644 sim65/test/C64KernalStubs.kt create mode 100644 sim65/test/Test6502TestSuite.kt diff --git a/sim65/build.gradle b/sim65/build.gradle index b29d0ca45..aba9f77a2 100644 --- a/sim65/build.gradle +++ b/sim65/build.gradle @@ -97,8 +97,11 @@ test { // Show test results. testLogging { - events "passed", "skipped", "failed" + events "failed" } + systemProperties['junit.jupiter.execution.parallel.enabled'] = true + systemProperties['junit.jupiter.execution.parallel.mode.default'] = 'concurrent' + maxParallelForks = Runtime.runtime.availableProcessors().intdiv(2) ?: 1 } diff --git a/sim65/src/C64KernalStubs.kt b/sim65/src/C64KernalStubs.kt deleted file mode 100644 index caf6e9a33..000000000 --- a/sim65/src/C64KernalStubs.kt +++ /dev/null @@ -1,47 +0,0 @@ -package sim65 - -import sim65.components.Address -import sim65.components.Cpu6502 -import sim65.components.ICpu -import sim65.components.Ram -import kotlin.system.exitProcess - -object C64KernalStubs { - - lateinit var ram: Ram - - fun handleBreakpoint(cpu: ICpu, pc: Address) { - cpu as Cpu6502 - when(pc) { - 0xffd2 -> { - // CHROUT - ram[0x030c] = 0 - val char = Petscii.decodePetscii(listOf(cpu.A.toShort()), true).first() - if(char==13.toChar()) - println() - else if(char in ' '..'~') - print(char) - cpu.currentOpcode = 0x60 // rts to end the stub - } - 0xffe4 -> { - // GETIN - print("[Input required:] ") - val s = readLine() - if(s.isNullOrEmpty()) - cpu.A = 3 - else - cpu.A = Petscii.encodePetscii(s, true).first().toInt() - cpu.currentOpcode = 0x60 // rts to end the stub - } - 0xe16f -> { - // LOAD/VERIFY - val loc = ram[0xbb].toInt() or (this.ram[0xbc].toInt() shl 8) - val len = ram[0xb7].toInt() - val filename = Petscii.decodePetscii((loc until loc+len).map { ram[it] }.toList(), true).toLowerCase() - ram.loadPrg("c64tests/$filename") - cpu.popStackAddr() - cpu.PC = 0x0816 // continue in next module - } - } - } -} diff --git a/sim65/src/Sim65Main.kt b/sim65/src/Sim65Main.kt index 7af939813..b63f6c7f9 100644 --- a/sim65/src/Sim65Main.kt +++ b/sim65/src/Sim65Main.kt @@ -1,63 +1,89 @@ package sim65 import kotlinx.cli.* -import sim65.C64KernalStubs.handleBreakpoint import sim65.components.* -import sim65.components.Cpu6502.Companion.IRQ_vector -import sim65.components.Cpu6502.Companion.RESET_vector +import sim65.components.Cpu6502.Companion.hexB import kotlin.system.exitProcess fun main(args: Array) { - printSoftwareHeader() - startSimulator(args) + printSoftwareHeader2() + startSimulator2(args) } -internal fun printSoftwareHeader() { +internal fun printSoftwareHeader2() { val buildVersion = object {}.javaClass.getResource("/version.txt").readText().trim() println("\nSim65 6502 cpu simulator v$buildVersion by Irmen de Jong (irmen@razorvine.net)") println("This software is licensed under the GNU GPL 3.0, see https://www.gnu.org/licenses/gpl.html\n") } -private fun startSimulator(args: Array) { +private fun startSimulator2(args: Array) { + val bootRom = listOf( + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0,0,0, + 0x00,0x90, // NMI vector + 0x00,0x10, // RESET vector + 0x00,0xa0 // IRQ vector + ).toTypedArray() - val cpu = Cpu6502(stopOnBrk = false) - cpu.tracing = false - cpu.breakpoint(0xffd2, ::handleBreakpoint) - cpu.breakpoint(0xffe4, ::handleBreakpoint) - cpu.breakpoint(0xe16f, ::handleBreakpoint) + val cpu = Cpu6502(true) + cpu.tracing = true // create the system bus and add device to it. // note that the order is relevant w.r.t. where reads and writes are going. - val ram = Ram(0, 0xffff) - ram.set(0x02, 0) - ram.set(0xa002, 0) - ram.set(0xa003, 0x80) - ram.set(IRQ_vector, 0x48) - ram.set(IRQ_vector+1, 0xff) - ram.set(RESET_vector, 0x01) - ram.set(RESET_vector+1, 0x08) - ram.set(0x01fe, 0xff) - ram.set(0x01ff, 0x7f) - ram.set(0x8000, 2) - ram.set(0xa474, 2) - ram.loadPrg("c64tests/nopn") - C64KernalStubs.ram = ram - val bus = Bus() bus.add(cpu) + bus.add(Rom(0xff00, 0xffff, bootRom)) + bus.add(Parallel(0xd000, 0xd001)) + bus.add(Timer(0xd100, 0xd103)) + val ram = Ram(0, 0xffff) bus.add(ram) + bus.reset() - require(cpu.SP==0xfd) - require(cpu.Status.asByte().toInt()==0b00100100) + ram.load("sim65/test/testfiles/ram.bin", 0x8000) + ram.load("sim65/test/testfiles/bcdtest.bin", 0x1000) + //ram.dump(0x8000, 0x802f) + //cpu.disassemble(ram, 0x8000, 0x802f) try { while (true) { bus.clock() } } catch(e: InstructionError) { - println(">>> INSTRUCTION ERROR: ${e.message}") + } + + if(ram[0x0400] ==0.toShort()) + println("BCD TEST: OK!") + else { + val code = ram[0x0400] + val v1 = ram[0x0401] + val v2 = ram[0x0402] + val predictedA = ram[0x00fc] + val actualA = ram[0x00fd] + val predictedF = ram[0x00fe] + val actualF = ram[0x00ff] + println("BCD TEST: FAIL!! code=${hexB(code)} value1=${hexB(v1)} value2=${hexB(v2)}") + println(" predictedA=${hexB(predictedA)}") + println(" actualA=${hexB(actualA)}") + println(" predictedF=${predictedF.toString(2).padStart(8,'0')}") + println(" actualF=${actualF.toString(2).padStart(8,'0')}") + } + } diff --git a/sim65/src/Sim65MainBCDtest.kt b/sim65/src/Sim65MainBCDtest.kt deleted file mode 100644 index b63f6c7f9..000000000 --- a/sim65/src/Sim65MainBCDtest.kt +++ /dev/null @@ -1,89 +0,0 @@ -package sim65 - -import kotlinx.cli.* -import sim65.components.* -import sim65.components.Cpu6502.Companion.hexB -import kotlin.system.exitProcess - - -fun main(args: Array) { - printSoftwareHeader2() - startSimulator2(args) -} - -internal fun printSoftwareHeader2() { - val buildVersion = object {}.javaClass.getResource("/version.txt").readText().trim() - println("\nSim65 6502 cpu simulator v$buildVersion by Irmen de Jong (irmen@razorvine.net)") - println("This software is licensed under the GNU GPL 3.0, see https://www.gnu.org/licenses/gpl.html\n") -} - - -private fun startSimulator2(args: Array) { - val bootRom = listOf( - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0,0,0, - 0x00,0x90, // NMI vector - 0x00,0x10, // RESET vector - 0x00,0xa0 // IRQ vector - ).toTypedArray() - - val cpu = Cpu6502(true) - cpu.tracing = true - - // create the system bus and add device to it. - // note that the order is relevant w.r.t. where reads and writes are going. - val bus = Bus() - bus.add(cpu) - bus.add(Rom(0xff00, 0xffff, bootRom)) - bus.add(Parallel(0xd000, 0xd001)) - bus.add(Timer(0xd100, 0xd103)) - val ram = Ram(0, 0xffff) - bus.add(ram) - - bus.reset() - - ram.load("sim65/test/testfiles/ram.bin", 0x8000) - ram.load("sim65/test/testfiles/bcdtest.bin", 0x1000) - //ram.dump(0x8000, 0x802f) - //cpu.disassemble(ram, 0x8000, 0x802f) - - try { - while (true) { - bus.clock() - } - } catch(e: InstructionError) { - - } - - if(ram[0x0400] ==0.toShort()) - println("BCD TEST: OK!") - else { - val code = ram[0x0400] - val v1 = ram[0x0401] - val v2 = ram[0x0402] - val predictedA = ram[0x00fc] - val actualA = ram[0x00fd] - val predictedF = ram[0x00fe] - val actualF = ram[0x00ff] - println("BCD TEST: FAIL!! code=${hexB(code)} value1=${hexB(v1)} value2=${hexB(v2)}") - println(" predictedA=${hexB(predictedA)}") - println(" actualA=${hexB(actualA)}") - println(" predictedF=${predictedF.toString(2).padStart(8,'0')}") - println(" actualF=${actualF.toString(2).padStart(8,'0')}") - } - -} diff --git a/sim65/src/components/Cpu6502.kt b/sim65/src/components/Cpu6502.kt index e618d2157..ca6285f46 100644 --- a/sim65/src/components/Cpu6502.kt +++ b/sim65/src/components/Cpu6502.kt @@ -13,7 +13,7 @@ interface ICpu { fun breakpoint(address: Address, action: (cpu: ICpu, pc: Address) -> Unit) var tracing: Boolean - val totalCycles: Int + val totalCycles: Long } // TODO: add the optional additional cycles to certain instructions and addressing modes @@ -23,7 +23,7 @@ interface ICpu { class Cpu6502(private val stopOnBrk: Boolean) : BusComponent(), ICpu { override var tracing: Boolean = false - override var totalCycles: Int = 0 + override var totalCycles: Long = 0 private set companion object { diff --git a/c64tests/0start b/sim65/test/6502testsuite/0start similarity index 100% rename from c64tests/0start rename to sim65/test/6502testsuite/0start diff --git a/c64tests/_Test Suite 2.15.txt b/sim65/test/6502testsuite/_Test Suite 2.15.txt similarity index 100% rename from c64tests/_Test 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sim65/test/6502testsuite/trap7 diff --git a/c64tests/trap8 b/sim65/test/6502testsuite/trap8 similarity index 100% rename from c64tests/trap8 rename to sim65/test/6502testsuite/trap8 diff --git a/c64tests/trap9 b/sim65/test/6502testsuite/trap9 similarity index 100% rename from c64tests/trap9 rename to sim65/test/6502testsuite/trap9 diff --git a/c64tests/tsxn b/sim65/test/6502testsuite/tsxn similarity index 100% rename from c64tests/tsxn rename to sim65/test/6502testsuite/tsxn diff --git a/c64tests/txan b/sim65/test/6502testsuite/txan similarity index 100% rename from c64tests/txan rename to sim65/test/6502testsuite/txan diff --git a/c64tests/txsn b/sim65/test/6502testsuite/txsn similarity index 100% rename from c64tests/txsn rename to sim65/test/6502testsuite/txsn diff --git a/c64tests/tyan b/sim65/test/6502testsuite/tyan similarity index 100% rename from c64tests/tyan rename to sim65/test/6502testsuite/tyan diff --git a/sim65/test/C64KernalStubs.kt b/sim65/test/C64KernalStubs.kt new file mode 100644 index 000000000..92f2c3389 --- /dev/null +++ b/sim65/test/C64KernalStubs.kt @@ -0,0 +1,49 @@ +import sim65.Petscii +import sim65.components.Address +import sim65.components.Cpu6502 +import sim65.components.ICpu +import sim65.components.Ram + +class C64KernalStubs(private val ram: Ram) { + + fun handleBreakpoint(cpu: ICpu, pc: Address) { + cpu as Cpu6502 + when(pc) { + 0xffd2 -> { + // CHROUT + ram[0x030c] = 0 + val char = Petscii.decodePetscii(listOf(cpu.A.toShort()), true).first() + if(char==13.toChar()) + println() + else if(char in ' '..'~') + print(char) + cpu.currentOpcode = 0x60 // rts to end the stub + } + 0xffe4 -> { + // GETIN + throw InputRequired() +// print("[Input required:] ") +// val s = readLine() +// if(s.isNullOrEmpty()) +// cpu.A = 3 +// else +// cpu.A = Petscii.encodePetscii(s, true).first().toInt() +// cpu.currentOpcode = 0x60 // rts to end the stub + } + 0xe16f -> { + throw LoadNextPart() + // LOAD/VERIFY +// val loc = ram[0xbb].toInt() or (ram[0xbc].toInt() shl 8) +// val len = ram[0xb7].toInt() +// val filename = Petscii.decodePetscii((loc until loc + len).map { ram[it] }.toList(), true).toLowerCase() +// ram.loadPrg("test/6502testsuite/$filename") +// cpu.popStackAddr() +// cpu.PC = 0x0816 // continue in next module + } + } + } +} + +class LoadNextPart: Exception() +class InputRequired: Exception() + diff --git a/sim65/test/Test6502.kt b/sim65/test/Test6502.kt index 4e7ab5a0d..d4cdda308 100644 --- a/sim65/test/Test6502.kt +++ b/sim65/test/Test6502.kt @@ -275,7 +275,7 @@ class Test6502 : TestCommon6502() { writeMem(memory, 0, listOf(0x6c, 0xff, 0x00)) mpu.step() assertEquals(0x6c00, mpu.PC) - assertEquals(5+Cpu6502.resetCycles, mpu.totalCycles) + assertEquals((5+Cpu6502.resetCycles).toLong(), mpu.totalCycles) } // ORA Indexed, Indirect (Y) diff --git a/sim65/test/Test6502TestSuite.kt b/sim65/test/Test6502TestSuite.kt new file mode 100644 index 000000000..3bcb6332a --- /dev/null +++ b/sim65/test/Test6502TestSuite.kt @@ -0,0 +1,1382 @@ +import org.junit.jupiter.api.Disabled +import org.junit.jupiter.api.Test +import org.junit.jupiter.api.TestInstance +import org.junit.jupiter.api.fail +import sim65.components.Bus +import sim65.components.Cpu6502 +import sim65.components.InstructionError +import sim65.components.Ram + +@TestInstance(TestInstance.Lifecycle.PER_METHOD) +class Test6502TestSuite { + + val cpu: Cpu6502 = Cpu6502(stopOnBrk = false) + val ram = Ram(0, 0xffff) + val bus = Bus() + val kernalStubs = C64KernalStubs(ram) + + init { + cpu.tracing = false + cpu.breakpoint(0xffd2) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) } + cpu.breakpoint(0xffe4) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) } + cpu.breakpoint(0xe16f) { cpu, pc -> kernalStubs.handleBreakpoint(cpu, pc) } + + // create the system bus and add device to it. + // note that the order is relevant w.r.t. where reads and writes are going. + ram.set(0x02, 0) + ram.set(0xa002, 0) + ram.set(0xa003, 0x80) + ram.set(Cpu6502.IRQ_vector, 0x48) + ram.set(Cpu6502.IRQ_vector + 1, 0xff) + ram.set(Cpu6502.RESET_vector, 0x01) + ram.set(Cpu6502.RESET_vector + 1, 0x08) + ram.set(0x01fe, 0xff) + ram.set(0x01ff, 0x7f) + ram.set(0x8000, 2) + ram.set(0xa474, 2) + + bus.add(cpu) + bus.add(ram) + } + + private fun runTest(testprogram: String) { + ram.loadPrg("test/6502testsuite/$testprogram") + bus.reset() + cpu.SP = 0xfd + cpu.Status.fromByte(0b00100100) + try { + while (cpu.totalCycles < 50000000L) { + bus.clock() + } + fail("test hangs") + } catch (e: InstructionError) { + println(">>> INSTRUCTION ERROR: ${e.message}") + } catch (le: LoadNextPart) { + return // test ok + } catch (ie: InputRequired) { + fail("test failed") + } + fail("test failed") + } + + @Test + fun test0start() { + runTest("0start") + } + + @Test + fun testAdca() { + runTest("adca") + } + + @Test + fun testAdcax() { + runTest("adcax") + } + + @Test + fun testAdcay() { + runTest("adcay") + } + + @Test + fun testAdcb() { + runTest("adcb") + } + + @Test + fun testAdcix() { + runTest("adcix") + } + + @Test + fun testAdciy() { + runTest("adciy") + } + + @Test + fun testAdcz() { + runTest("adcz") + } + + @Test + fun testAdczx() { + runTest("adczx") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAlrb() { + runTest("alrb") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAncb() { + runTest("ancb") + } + + @Test + fun testAnda() { + runTest("anda") + } + + @Test + fun testAndax() { + runTest("andax") + } + + @Test + fun testAnday() { + runTest("anday") + } + + @Test + fun testAndb() { + runTest("andb") + } + + @Test + fun testAndix() { + runTest("andix") + } + + @Test + fun testAndiy() { + runTest("andiy") + } + + @Test + fun testAndz() { + runTest("andz") + } + + @Test + fun testAndzx() { + runTest("andzx") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAneb() { + runTest("aneb") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testArrb() { + runTest("arrb") + } + + @Test + fun testAsla() { + runTest("asla") + } + + @Test + fun testAslax() { + runTest("aslax") + } + + @Test + fun testAsln() { + runTest("asln") + } + + @Test + fun testAslz() { + runTest("aslz") + } + + @Test + fun testAslzx() { + runTest("aslzx") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAsoa() { + runTest("asoa") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAsoax() { + runTest("asoax") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAsoay() { + runTest("asoay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAsoix() { + runTest("asoix") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAsoiy() { + runTest("asoiy") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAsoz() { + runTest("asoz") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAsozx() { + runTest("asozx") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAxsa() { + runTest("axsa") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAxsix() { + runTest("axsix") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAxsz() { + runTest("axsz") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testAxszy() { + runTest("axszy") + } + + @Test + fun testBccr() { + runTest("bccr") + } + + @Test + fun testBcsr() { + runTest("bcsr") + } + + @Test + fun testBeqr() { + runTest("beqr") + } + + @Test + fun testBita() { + runTest("bita") + } + + @Test + fun testBitz() { + runTest("bitz") + } + + @Test + fun testBmir() { + runTest("bmir") + } + + @Test + fun testBner() { + runTest("bner") + } + + @Test + fun testBplr() { + runTest("bplr") + } + + @Test + fun testBranchwrap() { + runTest("branchwrap") + } + + @Test + fun testBrkn() { + runTest("brkn") + } + + @Test + fun testBvcr() { + runTest("bvcr") + } + + @Test + fun testBvsr() { + runTest("bvsr") + } + + @Test + @Disabled("c64 specific component") + fun testCia1pb6() { + runTest("cia1pb6") + } + + @Test + @Disabled("c64 specific component") + fun testCia1pb7() { + runTest("cia1pb7") + } + + @Test + @Disabled("c64 specific component") + fun testCia1ta() { + runTest("cia1ta") + } + + @Test + @Disabled("c64 specific component") + fun testCia1tab() { + runTest("cia1tab") + } + + @Test + @Disabled("c64 specific component") + fun testCia1tb() { + runTest("cia1tb") + } + + @Test + @Disabled("c64 specific component") + fun testCia1tb123() { + runTest("cia1tb123") + } + + @Test + @Disabled("c64 specific component") + fun testCia2pb6() { + runTest("cia2pb6") + } + + @Test + @Disabled("c64 specific component") + fun testCia2pb7() { + runTest("cia2pb7") + } + + @Test + @Disabled("c64 specific component") + fun testCia2ta() { + runTest("cia2ta") + } + + @Test + @Disabled("c64 specific component") + fun testCia2tb() { + runTest("cia2tb") + } + + @Test + @Disabled("c64 specific component") + fun testCia2tb123() { + runTest("cia2tb123") + } + + @Test + fun testClcn() { + runTest("clcn") + } + + @Test + fun testCldn() { + runTest("cldn") + } + + @Test + fun testClin() { + runTest("clin") + } + + @Test + fun testClvn() { + runTest("clvn") + } + + @Test + fun testCmpa() { + runTest("cmpa") + } + + @Test + fun testCmpax() { + runTest("cmpax") + } + + @Test + fun testCmpay() { + runTest("cmpay") + } + + @Test + fun testCmpb() { + runTest("cmpb") + } + + @Test + fun testCmpix() { + runTest("cmpix") + } + + @Test + fun testCmpiy() { + runTest("cmpiy") + } + + @Test + fun testCmpz() { + runTest("cmpz") + } + + @Test + fun testCmpzx() { + runTest("cmpzx") + } + + @Test + fun testCntdef() { + runTest("cntdef") + } + + @Test + fun testCnto2() { + runTest("cnto2") + } + + @Test + @Disabled("c64 6510 specific component") + fun testCpuport() { + runTest("cpuport") + } + + @Test + @Disabled("todo: get all cycle times right") + fun testCputiming() { + runTest("cputiming") + } + + @Test + fun testCpxa() { + runTest("cpxa") + } + + @Test + fun testCpxb() { + runTest("cpxb") + } + + @Test + fun testCpxz() { + runTest("cpxz") + } + + @Test + fun testCpya() { + runTest("cpya") + } + + @Test + fun testCpyb() { + runTest("cpyb") + } + + @Test + fun testCpyz() { + runTest("cpyz") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testDcma() { + runTest("dcma") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testDcmax() { + runTest("dcmax") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testDcmay() { + runTest("dcmay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testDcmix() { + runTest("dcmix") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testDcmiy() { + runTest("dcmiy") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testDcmz() { + runTest("dcmz") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testDcmzx() { + runTest("dcmzx") + } + + @Test + fun testDeca() { + runTest("deca") + } + + @Test + fun testDecax() { + runTest("decax") + } + + @Test + fun testDecz() { + runTest("decz") + } + + @Test + fun testDeczx() { + runTest("deczx") + } + + @Test + fun testDexn() { + runTest("dexn") + } + + @Test + fun testDeyn() { + runTest("deyn") + } + + @Test + fun testEora() { + runTest("eora") + } + + @Test + fun testEorax() { + runTest("eorax") + } + + @Test + fun testEoray() { + runTest("eoray") + } + + @Test + fun testEorb() { + runTest("eorb") + } + + @Test + fun testEorix() { + runTest("eorix") + } + + @Test + fun testEoriy() { + runTest("eoriy") + } + + @Test + fun testEorz() { + runTest("eorz") + } + + @Test + fun testEorzx() { + runTest("eorzx") + } + + @Test + @Disabled("c64 specific component") + fun testFlipos() { + runTest("flipos") + } + + @Test + @Disabled("c64 specific component") + fun testIcr01() { + runTest("icr01") + } + + @Test + @Disabled("c64 specific component") + fun testImr() { + runTest("imr") + } + + @Test + fun testInca() { + runTest("inca") + } + + @Test + fun testIncax() { + runTest("incax") + } + + @Test + fun testIncz() { + runTest("incz") + } + + @Test + fun testInczx() { + runTest("inczx") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testInsa() { + runTest("insa") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testInsax() { + runTest("insax") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testInsay() { + runTest("insay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testInsix() { + runTest("insix") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testInsiy() { + runTest("insiy") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testInsz() { + runTest("insz") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testInszx() { + runTest("inszx") + } + + @Test + fun testInxn() { + runTest("inxn") + } + + @Test + fun testInyn() { + runTest("inyn") + } + + @Test + @Disabled("c64 specific component") + fun testIrq() { + runTest("irq") + } + + @Test + fun testJmpi() { + runTest("jmpi") + } + + @Test + fun testJmpw() { + runTest("jmpw") + } + + @Test + fun testJsrw() { + runTest("jsrw") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLasay() { + runTest("lasay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLaxa() { + runTest("laxa") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLaxay() { + runTest("laxay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLaxix() { + runTest("laxix") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLaxiy() { + runTest("laxiy") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLaxz() { + runTest("laxz") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLaxzy() { + runTest("laxzy") + } + + @Test + fun testLdaa() { + runTest("ldaa") + } + + @Test + fun testLdaax() { + runTest("ldaax") + } + + @Test + fun testLdaay() { + runTest("ldaay") + } + + @Test + fun testLdab() { + runTest("ldab") + } + + @Test + fun testLdaix() { + runTest("ldaix") + } + + @Test + fun testLdaiy() { + runTest("ldaiy") + } + + @Test + fun testLdaz() { + runTest("ldaz") + } + + @Test + fun testLdazx() { + runTest("ldazx") + } + + @Test + fun testLdxa() { + runTest("ldxa") + } + + @Test + fun testLdxay() { + runTest("ldxay") + } + + @Test + fun testLdxb() { + runTest("ldxb") + } + + @Test + fun testLdxz() { + runTest("ldxz") + } + + @Test + fun testLdxzy() { + runTest("ldxzy") + } + + @Test + fun testLdya() { + runTest("ldya") + } + + @Test + fun testLdyax() { + runTest("ldyax") + } + + @Test + fun testLdyb() { + runTest("ldyb") + } + + @Test + fun testLdyz() { + runTest("ldyz") + } + + @Test + fun testLdyzx() { + runTest("ldyzx") + } + + @Test + @Disabled("c64 specific component") + fun testLoadth() { + runTest("loadth") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLsea() { + runTest("lsea") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLseax() { + runTest("lseax") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLseay() { + runTest("lseay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLseix() { + runTest("lseix") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLseiy() { + runTest("lseiy") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLsez() { + runTest("lsez") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLsezx() { + runTest("lsezx") + } + + @Test + fun testLsra() { + runTest("lsra") + } + + @Test + fun testLsrax() { + runTest("lsrax") + } + + @Test + fun testLsrn() { + runTest("lsrn") + } + + @Test + fun testLsrz() { + runTest("lsrz") + } + + @Test + fun testLsrzx() { + runTest("lsrzx") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testLxab() { + runTest("lxab") + } + + @Test + @Disabled("c64 6510 specific component") + fun testMmu() { + runTest("mmu") + } + + @Test + @Disabled("c64 6510 specific component") + fun testMmufetch() { + runTest("mmufetch") + } + + @Test + fun testNmi() { + runTest("nmi") + } + + @Test + fun testNopa() { + runTest("nopa") + } + + @Test + fun testNopax() { + runTest("nopax") + } + + @Test + fun testNopb() { + runTest("nopb") + } + + @Test + fun testNopn() { + runTest("nopn") + } + + @Test + fun testNopz() { + runTest("nopz") + } + + @Test + fun testNopzx() { + runTest("nopzx") + } + + @Test + @Disabled("c64 specific component") + fun testOneshot() { + runTest("oneshot") + } + + @Test + fun testOraa() { + runTest("oraa") + } + + @Test + fun testOraax() { + runTest("oraax") + } + + @Test + fun testOraay() { + runTest("oraay") + } + + @Test + fun testOrab() { + runTest("orab") + } + + @Test + fun testOraix() { + runTest("oraix") + } + + @Test + fun testOraiy() { + runTest("oraiy") + } + + @Test + fun testOraz() { + runTest("oraz") + } + + @Test + fun testOrazx() { + runTest("orazx") + } + + @Test + fun testPhan() { + runTest("phan") + } + + @Test + fun testPhpn() { + runTest("phpn") + } + + @Test + fun testPlan() { + runTest("plan") + } + + @Test + fun testPlpn() { + runTest("plpn") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRlaa() { + runTest("rlaa") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRlaax() { + runTest("rlaax") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRlaay() { + runTest("rlaay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRlaix() { + runTest("rlaix") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRlaiy() { + runTest("rlaiy") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRlaz() { + runTest("rlaz") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRlazx() { + runTest("rlazx") + } + + @Test + fun testRola() { + runTest("rola") + } + + @Test + fun testRolax() { + runTest("rolax") + } + + @Test + fun testRoln() { + runTest("roln") + } + + @Test + fun testRolz() { + runTest("rolz") + } + + @Test + fun testRolzx() { + runTest("rolzx") + } + + @Test + fun testRora() { + runTest("rora") + } + + @Test + fun testRorax() { + runTest("rorax") + } + + @Test + fun testRorn() { + runTest("rorn") + } + + @Test + fun testRorz() { + runTest("rorz") + } + + @Test + fun testRorzx() { + runTest("rorzx") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRraa() { + runTest("rraa") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRraax() { + runTest("rraax") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRraay() { + runTest("rraay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRraix() { + runTest("rraix") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRraiy() { + runTest("rraiy") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRraz() { + runTest("rraz") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testRrazx() { + runTest("rrazx") + } + + @Test + fun testRtin() { + runTest("rtin") + } + + @Test + fun testRtsn() { + runTest("rtsn") + } + + @Test + fun testSbca() { + runTest("sbca") + } + + @Test + fun testSbcax() { + runTest("sbcax") + } + + @Test + fun testSbcay() { + runTest("sbcay") + } + + @Test + fun testSbcb() { + runTest("sbcb") + } + + @Test + fun testSbcb_eb() { + runTest("sbcb(eb)") + } + + @Test + fun testSbcix() { + runTest("sbcix") + } + + @Test + fun testSbciy() { + runTest("sbciy") + } + + @Test + fun testSbcz() { + runTest("sbcz") + } + + @Test + fun testSbczx() { + runTest("sbczx") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testSbxb() { + runTest("sbxb") + } + + @Test + fun testSecn() { + runTest("secn") + } + + @Test + fun testSedn() { + runTest("sedn") + } + + @Test + fun testSein() { + runTest("sein") + } + + @Test + @Disabled("not yet implemented- illegal instruction sha/ahx") + fun testShaay() { + runTest("shaay") + } + + @Test + @Disabled("not yet implemented- illegal instruction sha/ahx") + fun testShaiy() { + runTest("shaiy") + } + + @Test + @Disabled("not yet implemented- illegal instruction shs/tas") + fun testShsay() { + runTest("shsay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testShxay() { + runTest("shxay") + } + + @Test + @Disabled("not yet implemented- illegal instruction") + fun testShyax() { + runTest("shyax") + } + + @Test + fun testStaa() { + runTest("staa") + } + + @Test + fun testStaax() { + runTest("staax") + } + + @Test + fun testStaay() { + runTest("staay") + } + + @Test + fun testStaix() { + runTest("staix") + } + + @Test + fun testStaiy() { + runTest("staiy") + } + + @Test + fun testStaz() { + runTest("staz") + } + + @Test + fun testStazx() { + runTest("stazx") + } + + @Test + fun testStxa() { + runTest("stxa") + } + + @Test + fun testStxz() { + runTest("stxz") + } + + @Test + fun testStxzy() { + runTest("stxzy") + } + + @Test + fun testStya() { + runTest("stya") + } + + @Test + fun testStyz() { + runTest("styz") + } + + @Test + fun testStyzx() { + runTest("styzx") + } + + @Test + fun testTaxn() { + runTest("taxn") + } + + @Test + fun testTayn() { + runTest("tayn") + } + + @Test + fun testTsxn() { + runTest("tsxn") + } + + @Test + fun testTxan() { + runTest("txan") + } + + @Test + fun testTxsn() { + runTest("txsn") + } + + @Test + fun testTyan() { + runTest("tyan") + } + +} diff --git a/sim65/test/TestCommon6502.kt b/sim65/test/TestCommon6502.kt index f8f6eaf19..7171d3194 100644 --- a/sim65/test/TestCommon6502.kt +++ b/sim65/test/TestCommon6502.kt @@ -1923,7 +1923,7 @@ abstract class TestCommon6502 { mpu.A = 0xFF mpu.step() assertEquals(0x0002, mpu.PC) - assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles) + assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt()) assertTrue(mpu.Status.N) } @@ -1936,7 +1936,7 @@ abstract class TestCommon6502 { mpu.A = 0xFF mpu.step() assertEquals(0x0002, mpu.PC) - assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles) + assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt()) assertFalse(mpu.Status.N) } @@ -1949,7 +1949,7 @@ abstract class TestCommon6502 { mpu.A = 0xFF mpu.step() assertEquals(0x0002, mpu.PC) - assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles) + assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt()) assertTrue(mpu.Status.V) } @@ -1962,7 +1962,7 @@ abstract class TestCommon6502 { mpu.A = 0xFF mpu.step() assertEquals(0x0002, mpu.PC) - assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles) + assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt()) assertFalse(mpu.Status.V) } @@ -1975,7 +1975,7 @@ abstract class TestCommon6502 { mpu.A = 0x01 mpu.step() assertEquals(0x0002, mpu.PC) - assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles) + assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt()) assertTrue(mpu.Status.Z) assertEquals(0x01, mpu.A) assertEquals(0x00, memory[0x0010]) @@ -1990,7 +1990,7 @@ abstract class TestCommon6502 { mpu.A = 0x01 mpu.step() assertEquals(0x0002, mpu.PC) - assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles) + assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt()) assertFalse(mpu.Status.Z) // result of AND is non-zero assertEquals(0x01, mpu.A) assertEquals(0x01, memory[0x0010]) @@ -2005,7 +2005,7 @@ abstract class TestCommon6502 { mpu.A = 0x01 mpu.step() assertEquals(0x0002, mpu.PC) - assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles) + assertEquals(3 + Cpu6502.resetCycles, mpu.totalCycles.toInt()) assertTrue(mpu.Status.Z) // result of AND is zero assertEquals(0x01, mpu.A) assertEquals(0x00, memory[0x0010])