diff --git a/codeGeneration/src/prog8/compiler/target/c64/C64MachineDefinition.kt b/codeGeneration/src/prog8/compiler/target/c64/C64MachineDefinition.kt index e4e127ee3..91b136de7 100644 --- a/codeGeneration/src/prog8/compiler/target/c64/C64MachineDefinition.kt +++ b/codeGeneration/src/prog8/compiler/target/c64/C64MachineDefinition.kt @@ -1,5 +1,6 @@ package prog8.compiler.target.c64 +import prog8.ast.base.DataType import prog8.compiler.target.cbm.Mflpt5 import prog8.compiler.target.cbm.viceMonListPostfix import prog8.compilerinterface.* @@ -56,6 +57,7 @@ class C64MachineDefinition: IMachineDefinition { } override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0xd000u..0xdfffu + override fun getPreallocatedZeropageVars(): Map> = emptyMap() override fun initializeZeropage(compilerOptions: CompilationOptions) { zeropage = C64Zeropage(compilerOptions) diff --git a/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/AsmGen.kt b/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/AsmGen.kt index eff0f6055..63c08605a 100644 --- a/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/AsmGen.kt +++ b/codeGeneration/src/prog8/compiler/target/cpu6502/codegen/AsmGen.kt @@ -41,7 +41,7 @@ class AsmGen(private val program: Program, private val assemblyLines = mutableListOf() private val globalFloatConsts = mutableMapOf() // all float values in the entire program (value -> varname) - private val allocatedZeropageVariables = mutableMapOf>() + private val allocatedZeropageVariables = compTarget.machine.getPreallocatedZeropageVars().toMutableMap() private val breakpointLabels = mutableListOf() private val forloopsAsmGen = ForLoopsAsmGen(program, this) private val postincrdecrAsmGen = PostIncrDecrAsmGen(program, this) @@ -1530,7 +1530,8 @@ $label nop""") } } - internal fun isZpVar(scopedName: String): Boolean = scopedName in allocatedZeropageVariables + internal fun isZpVar(scopedName: String): Boolean = + scopedName in allocatedZeropageVariables internal fun isZpVar(variable: IdentifierReference): Boolean { val vardecl = variable.targetVarDecl(program)!! diff --git a/codeGeneration/src/prog8/compiler/target/cx16/CX16MachineDefinition.kt b/codeGeneration/src/prog8/compiler/target/cx16/CX16MachineDefinition.kt index eac7dfcaf..d9e512d80 100644 --- a/codeGeneration/src/prog8/compiler/target/cx16/CX16MachineDefinition.kt +++ b/codeGeneration/src/prog8/compiler/target/cx16/CX16MachineDefinition.kt @@ -1,5 +1,6 @@ package prog8.compiler.target.cx16 +import prog8.ast.base.DataType import prog8.compiler.target.cbm.Mflpt5 import prog8.compiler.target.cbm.viceMonListPostfix import prog8.compilerinterface.* @@ -67,6 +68,18 @@ class CX16MachineDefinition: IMachineDefinition { } override fun isIOAddress(address: UInt): Boolean = address==0u || address==1u || address in 0x9f00u..0x9fffu + override fun getPreallocatedZeropageVars(): Map> { + val vars = mutableMapOf>() + for(reg in 0..15) { + vars["cx16.r${reg}"] = (2+reg*2).toUInt() to DataType.UWORD // cx16.r0 .. cx16.r15 + vars["cx16.r${reg}s"] = (2+reg*2).toUInt() to DataType.WORD // cx16.r0s .. cx16.r15s + vars["cx16.r${reg}L"] = (2+reg*2).toUInt() to DataType.UBYTE // cx16.r0L .. cx16.r15L + vars["cx16.r${reg}H"] = (3+reg*2).toUInt() to DataType.UBYTE // cx16.r0H .. cx16.r15H + vars["cx16.r${reg}sL"] = (2+reg*2).toUInt() to DataType.BYTE // cx16.r0sL .. cx16.r15sL + vars["cx16.r${reg}sH"] = (3+reg*2).toUInt() to DataType.BYTE // cx16.r0sH .. cx16.r15sH + } + return vars + } override fun initializeZeropage(compilerOptions: CompilationOptions) { zeropage = CX16Zeropage(compilerOptions) diff --git a/compilerInterfaces/src/prog8/compilerinterface/IMachineDefinition.kt b/compilerInterfaces/src/prog8/compilerinterface/IMachineDefinition.kt index 22e61ec95..333cacb85 100644 --- a/compilerInterfaces/src/prog8/compilerinterface/IMachineDefinition.kt +++ b/compilerInterfaces/src/prog8/compilerinterface/IMachineDefinition.kt @@ -1,5 +1,6 @@ package prog8.compilerinterface +import prog8.ast.base.DataType import java.nio.file.Path @@ -33,4 +34,5 @@ interface IMachineDefinition { fun importLibs(compilerOptions: CompilationOptions, compilationTargetName: String): List fun launchEmulator(selectedEmulator: Int, programNameWithPath: Path) fun isIOAddress(address: UInt): Boolean + fun getPreallocatedZeropageVars(): Map> } diff --git a/docs/source/todo.rst b/docs/source/todo.rst index b336174b5..86c25d631 100644 --- a/docs/source/todo.rst +++ b/docs/source/todo.rst @@ -3,9 +3,8 @@ TODO For next compiler release (7.5) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -fix: cx16.r0 isn't seen as zeropage so @(cx16.r0) still copies it to temp zp -fix: when statements generate unneeded branches to choice_end? -fix: amountOfRtsInAsm() look in subscopes too +- fix: amountOfRtsInAsm() look in subscopes too +- fix: when statements generate unneeded branches to choice_end? diff --git a/examples/test.p8 b/examples/test.p8 index 664869861..0b2820679 100644 --- a/examples/test.p8 +++ b/examples/test.p8 @@ -4,16 +4,6 @@ main { sub start() { - str text = "\x00\xff\u0041A" - txt.print(text) - txt.nl() - txt.print_ub(text[0]) - txt.spc() - txt.print_ub(text[1]) - txt.spc() - txt.print_ub(text[2]) - txt.spc() - txt.print_ub(text[3]) - txt.nl() + ubyte @shared bb = @(cx16.r0) } }