diff --git a/codeGenCpu6502/src/prog8/codegen/cpu6502/AsmOptimizer.kt b/codeGenCpu6502/src/prog8/codegen/cpu6502/AsmOptimizer.kt
index 5d16bcda8..9721144e6 100644
--- a/codeGenCpu6502/src/prog8/codegen/cpu6502/AsmOptimizer.kt
+++ b/codeGenCpu6502/src/prog8/codegen/cpu6502/AsmOptimizer.kt
@@ -715,9 +715,9 @@ private fun optimizeTSBtoRegularOr(linesByFour: Sequence<List<IndexedValue<Strin
             val operand2 = second.substring(3)
             val operand3 = third.substring(3)
             if(operand1!=operand2 && operand2==operand3) {
-                mods.add(Modification(lines[0].index, false, "  lda  $operand2  ; op2"))
-                mods.add(Modification(lines[1].index, false, "  ora  $operand1  ; op1"))
-                mods.add(Modification(lines[2].index, false, "  sta  $operand2  ; op2"))
+                mods.add(Modification(lines[0].index, false, "  lda  $operand2"))
+                mods.add(Modification(lines[1].index, false, "  ora  $operand1"))
+                mods.add(Modification(lines[2].index, false, "  sta  $operand2"))
             }
         }
     }
diff --git a/codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AugmentableAssignmentAsmGen.kt b/codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AugmentableAssignmentAsmGen.kt
index 4f739f438..efd6d943d 100644
--- a/codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AugmentableAssignmentAsmGen.kt
+++ b/codeGenCpu6502/src/prog8/codegen/cpu6502/assignment/AugmentableAssignmentAsmGen.kt
@@ -1088,11 +1088,17 @@ $shortcutLabel:""")
 
         if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
             if(operator=="&" && value is PtPrefix && value.operator=="~") {
-                // M &= ~A  -->  use special TRB 65c02 instruction for that
+                // M &= ~A  -->  use TRB 65c02 instruction for that
                 asmgen.assignExpressionToRegister(value.value, RegisterOrPair.A, dt in SignedDatatypes)
                 asmgen.out("  trb  $name")
                 return
             }
+            else if(operator=="|") {
+                // M |= A --> use TSB 65c02 instruction for that
+                asmgen.assignExpressionToRegister(value, RegisterOrPair.A, dt in SignedDatatypes)
+                asmgen.out("  tsb  $name")
+                return
+            }
         }
 
         // normal evaluation
@@ -1106,7 +1112,7 @@ $shortcutLabel:""")
 
         if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
             if(operator=="|") {
-                // M |= A  -->  use special TSB 65c02 instruction for that
+                // M |= A  -->  use TSB 65c02 instruction for that
                 asmgen.out("  lda  $otherName |  tsb  $name")
                 return
             }
@@ -1661,7 +1667,7 @@ $shortcutLabel:""")
     }
 
     private fun immediateOrInplace(name: String, value: Int) {
-        if(asmgen.isTargetCpu(CpuType.CPU65c02) && ((value and (value-1))==0)) {
+        if(asmgen.isTargetCpu(CpuType.CPU65c02)) {
             asmgen.out(" lda  #$value |  tsb  $name")       // set bit
         } else  {
             asmgen.out(" lda  $name |  ora  #$value |  sta  $name")
diff --git a/examples/test.p8 b/examples/test.p8
index 223868820..05e08e345 100644
--- a/examples/test.p8
+++ b/examples/test.p8
@@ -5,114 +5,44 @@
 
 main {
     sub start() {
-        ubyte @shared variable
+        ubyte @shared v1,v2,v3
+        v1 = %10011001
+        v2 = %10101010
+        v3 = %00111100
 
-        variable = 0
-        while variable & %10000000 == 0 {
-            cx16.r0L++
-            variable = 128
-        }
-        txt.chrout('1')
-        while variable & %10000000 != 0 {
-            cx16.r0L++
-            variable = 0
-        }
-        txt.chrout('2')
-        while variable & %01000000 == 0 {
-            cx16.r0L++
-            variable = 64
-        }
-        txt.chrout('3')
-        while variable & %01000000 != 0 {
-            cx16.r0L++
-            variable=0
-        }
-        txt.chrout('4')
-        variable = 255
-        while variable & %10000000 == 0 {
-        }
-        while variable & %01000000 == 0 {
-        }
-        txt.chrout('5')
-        variable = 0
-        while variable & %10000000 != 0 {
-        }
-        while variable & %01000000 != 0 {
-        }
-        txt.chrout('6')
-        txt.chrout('\n')
+        v1 &= %00011111
+        v1++
+        txt.print_ubbin(v1, true)
+        txt.nl()
 
-        variable = 0
-        cx16.r0L++
-        if variable & %10000000 == 0 {
-            txt.print("bit 7 not set\n")
-        }
-        if variable & %10000000 != 0 {
-            txt.print("bit 7 set\n")
-        }
-        if variable & %10000000 == 0 {
-            txt.print("bit 7 not set\n")
-        } else {
-            txt.print("bit 7 set\n")
-        }
-        if variable & %10000000 != 0 {
-            txt.print("bit 7 set\n")
-        } else {
-            txt.print("bit 7 not set\n")
-        }
+        v1 &= ~v2
+        v1++
+        txt.print_ubbin(v1, true)
+        txt.nl()
 
-        variable = 128
-        cx16.r0L++
-        if variable & %10000000 == 0 {
-            txt.print("bit 7 not set\n")
-        }
-        if variable & %10000000 != 0 {
-            txt.print("bit 7 set\n")
-        }
-        if variable & %10000000 == 0 {
-            txt.print("bit 7 not set\n")
-        } else {
-            txt.print("bit 7 set\n")
-        }
-        if variable & %10000000 != 0 {
-            txt.print("bit 7 set\n")
-        } else {
-            txt.print("bit 7 not set\n")
-        }
+        v1 |= 100
+        v1++
+        txt.print_ubbin(v1, true)
+        txt.nl()
 
-        if variable & %01000000 == 0 {
-            txt.print("bit 6 not set\n")
-        }
-        if variable & %01000000 != 0 {
-            txt.print("bit 6 set\n")
-        }
-        if variable & %01000000 == 0 {
-            txt.print("bit 6 not set\n")
-        } else {
-            txt.print("bit 6 set\n")
-        }
-        if variable & %01000000 != 0 {
-            txt.print("bit 6 set\n")
-        } else {
-            txt.print("bit 6 not set\n")
-        }
-        variable = %01000000
-        cx16.r0L++
-        if variable & %01000000 == 0 {
-            txt.print("bit 6 not set\n")
-        }
-        if variable & %01000000 != 0 {
-            txt.print("bit 6 set\n")
-        }
-        if variable & %01000000 == 0 {
-            txt.print("bit 6 not set\n")
-        } else {
-            txt.print("bit 6 set\n")
-        }
-        if variable & %01000000 != 0 {
-            txt.print("bit 6 set\n")
-        } else {
-            txt.print("bit 6 not set\n")
-        }
+        v1 |= v2
+        v1++
+        txt.print_ubbin(v1, true)
+        txt.nl()
+
+        v1 |= v2 & v3
+        v1++
+        txt.print_ubbin(v1, true)
+        txt.nl()
+
+        v1 &= v2|v3
+        v1++
+        txt.print_ubbin(v1, true)
+        txt.nl()
+
+        v1 &= ~(v2|v3)
+        v1++
+        txt.print_ubbin(v1, true)
+        txt.nl()
     }
 }